From ae079c1fc5d990ba55714d4b3a51b19f96edaec4 Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期四, 24 四月 2025 16:01:43 +0800
Subject: [PATCH] 改为中断来低电平触发发送当前扫描数据，3s内扫描不到的会退出，串口来55 AA 75 70 64 61 74 65，进入升级模式
---
01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/pan_lp.c | 134 ++++++++++++++++++++++++++++++++++++++++++--
1 files changed, 128 insertions(+), 6 deletions(-)
diff --git a/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/pan_lp.c b/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/pan_lp.c
index f961d7e..a1d92e1 100644
--- a/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/pan_lp.c
+++ b/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/pan_lp.c
@@ -1,14 +1,15 @@
#include "PanSeries.h"
#include "pan_lp.h"
#include "pan_clk.h"
+#include "comm_prf.h"
extern const uint32_t PanFlashLineMode;
extern const bool PanFlashEnhanceEnable;
/**
-* @brief This function enable gpio p56 wake up
+* @brief This function enable gpio p56 wake up
* @param[in] ana: where ana is analog module
-* @param[in] WkEdge: wake up edge select,0-->low,1-->high
+* @param[in] WkEdge: wake up edge select,0-->low,1-->high
* @return none
*/
void LP_SetExternalWake(ANA_T *ana,uint8_t WkEdge)
@@ -85,7 +86,6 @@
*
* @return none
*/
-
void LP_SetSleepMode(ANA_T *ana,uint8_t mode)
{
uint32_t tmp_reg;
@@ -94,6 +94,128 @@
tmp_reg &= ~(ANAC_FL_SLEEP_MODE_SEL_Msk);
tmp_reg |= (mode << ANAC_FL_SLEEP_MODE_SEL_Pos);
ana->LP_FL_CTRL_3V = tmp_reg;
+}
+
+__STATIC_FORCEINLINE void PHY_FifoFlush(void)
+{
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FLUSH, 0x1);
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FLUSH, 0x0);
+
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_FLUSH, 0x1);
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_FLUSH, 0x0);
+}
+
+uint32_t PHY_WriteCfgFifoBatchCopy(const uint32_t *command, const uint32_t cmd_len, uint32_t *ptr_rsp_value)
+{
+ volatile uint32_t reg = 0;
+ uint32_t time_out = 0, cmd_idx = 0;
+ uint32_t rsp_len = 0;
+
+ if (0 == cmd_len)
+ {
+ goto fun_ext;
+ }
+
+ /* Flush the PHY Driver FIFO */
+ PHY_FifoFlush();
+
+ /* Trigger the FIFO */
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_TRG, 0x1);
+
+ do
+ {
+ do
+ {
+ /* check that the FIFO is empty */
+ reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FULL);
+ } while (reg == 1);
+
+ /* Write the commands to FIFO */
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY3, PHY_DRV_CFG_BUF_DIN, command[cmd_idx++]);
+
+ /* check that the Response buff is full */
+ reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_EMPTY);
+ if ((ptr_rsp_value != NULL) && (reg == 0))
+ {
+ /* read the response from FIFO */
+ ptr_rsp_value[rsp_len++] = PRI_RF_READ_REG_VALUE(PRI_RF, PHY4, PHY_DRV_RSP_BUF_DOUT);
+ }
+ } while (cmd_idx < cmd_len);
+
+ do
+ {
+ time_out++;
+ reg = PRI_RF_READ_REG_VALUE(PRI_RF, INTR1, IC_PHY_DRV_CFG_DONE);
+ } while (reg == 0);
+
+ /* check that the Response buff is full */
+ reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_EMPTY);
+
+ while ((ptr_rsp_value != NULL) && (reg == 0))
+ {
+ /* read the response from FIFO */
+ ptr_rsp_value[rsp_len++] = PRI_RF_READ_REG_VALUE(PRI_RF, PHY4, PHY_DRV_RSP_BUF_DOUT);
+ /* check that the Response buff is full */
+ reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_EMPTY);
+ }
+
+ /* Clear the interrupt */
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, INTCLR, IC_PHY_DRV_CFG_DONE_CLR, 1);
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, INTCLR, IC_PHY_DRV_CFG_DONE_CLR, 0);
+ PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_TRG, 0x0);
+
+fun_ext:
+
+ return rsp_len;
+}
+
+uint32_t PHY_SingleRegRead(uint32_t reg_addr)
+{
+ uint32_t reg;
+ uint32_t val;
+ uint32_t cmd[] = {
+ 0x00000013 | (reg_addr << 8),
+ };
+
+ // Backup AHB Clock Register and enable LL Clock
+ reg = CLK->AHB_CLK_CTRL;
+ CLK->AHB_CLK_CTRL |= CLK_AHBCLK_BLE32M_EN_Msk | CLK_AHBCLK_BLE32K_EN_Msk;
+
+ // Enable LL module for later phy operation
+ LLHWC_WRITE_MASK32_REG(REG_FILE_OFST, CTRL_MEM_SOFT_RST_N, CTRL_MEM_SOFT_RST_N_MSK, CTRL_MEM_SOFT_RST_N_SHFT, 0);
+ LLHWC_WRITE_MASK32_REG(REG_FILE_OFST, CTRL_MEM_SOFT_RST_N, CTRL_MEM_SOFT_RST_N_MSK, CTRL_MEM_SOFT_RST_N_SHFT, 1);
+ LLHWC_WRITE_MASK32_REG(REG_FILE_OFST, CTRL_PWR_MOD, CTRL_PWR_MOD_MSK, CTRL_PWR_MOD_SHFT, 1);
+
+ // Start to read phy register
+ PHY_WriteCfgFifoBatchCopy(cmd, sizeof(cmd) >> 2, &val);
+
+ // Restore AHB Clock Register
+ CLK->AHB_CLK_CTRL = reg;
+
+ return val;
+}
+
+void PHY_SingleRegWrite(uint32_t reg_addr, uint32_t reg_val)
+{
+ uint32_t reg;
+ uint32_t cmd[] = {
+ 0x00000012 | (reg_addr << 8) | (reg_val << 16),
+ };
+
+ // Backup AHB Clock Register and enable LL Clock
+ reg = CLK->AHB_CLK_CTRL;
+ CLK->AHB_CLK_CTRL |= CLK_AHBCLK_BLE32M_EN_Msk | CLK_AHBCLK_BLE32K_EN_Msk;
+
+ // Enable LL module for later phy operation
+ LLHWC_WRITE_MASK32_REG(REG_FILE_OFST, CTRL_MEM_SOFT_RST_N, CTRL_MEM_SOFT_RST_N_MSK, CTRL_MEM_SOFT_RST_N_SHFT, 0);
+ LLHWC_WRITE_MASK32_REG(REG_FILE_OFST, CTRL_MEM_SOFT_RST_N, CTRL_MEM_SOFT_RST_N_MSK, CTRL_MEM_SOFT_RST_N_SHFT, 1);
+ LLHWC_WRITE_MASK32_REG(REG_FILE_OFST, CTRL_PWR_MOD, CTRL_PWR_MOD_MSK, CTRL_PWR_MOD_SHFT, 1);
+
+ // Start to write phy register
+ PHY_WriteCfgFifoBatchCopy(cmd, sizeof(cmd) >> 2, NULL);
+
+ // Restore AHB Clock Register
+ CLK->AHB_CLK_CTRL = reg;
}
@@ -191,7 +313,7 @@
// Configure LP delay
ana->LP_DLY_CTRL_3V &= ~0x3ff;
- ana->LP_DLY_CTRL_3V |= 0x5;
+ ana->LP_DLY_CTRL_3V |= 0x7;
// Mask all interrupts
__disable_irq();
@@ -297,7 +419,7 @@
/* Set digital delay with 32k tick unit */
ana->LP_DLY_CTRL_3V &= ~0x3ff;
- ana->LP_DLY_CTRL_3V |= 5;
+ ana->LP_DLY_CTRL_3V |= 7;
/* Insure we are going to enter hw standby mode 1 */
LP_SetSleepMode(ana, LP_MODE_SEL_STANDBY_M1_MODE);
@@ -402,7 +524,7 @@
/* Set digital delay with 32k tick unit */
ANA->LP_DLY_CTRL_3V &= ~0x3ff;
- ANA->LP_DLY_CTRL_3V |= 5;
+ ANA->LP_DLY_CTRL_3V |= 7;
/* Insure we are going to enter hw standby mode 1 */
LP_SetSleepMode(ANA, LP_MODE_SEL_STANDBY_M0_MODE);
--
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