From ae079c1fc5d990ba55714d4b3a51b19f96edaec4 Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期四, 24 四月 2025 16:01:43 +0800
Subject: [PATCH] 改为中断来低电平触发发送当前扫描数据，3s内扫描不到的会退出，串口来55 AA 75 70 64 61 74 65，进入升级模式
---
01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/system_PANSeries.c | 56 +++++++++++++++++++++++---------------------------------
1 files changed, 23 insertions(+), 33 deletions(-)
diff --git a/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/system_PANSeries.c b/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/system_PANSeries.c
index ee17082..e93a20f 100644
--- a/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/system_PANSeries.c
+++ b/01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/system_PANSeries.c
@@ -23,7 +23,6 @@
*/
const uint32_t PanFlashLineMode = CONFIG_FLASH_LINE_MODE;
const bool PanFlashEnhanceEnable = false;
-uint32_t vec_remap_adr = 0x20007000;
/**
* @brief Setup the microcontroller system
@@ -35,10 +34,10 @@
void SystemInit(void)
{
ANA->CPU_ADDR_REMAP_CTRL =0;
-
+
// Speed up flash clock from default 16MHz to 32MHz
CLK_SetFlashClkDiv(CLK_FLASH_CLKDIV_1);
- // Switch flash to 4-Line mode
+ // Switch flash line mode
FMC_SetFlashMode(FLCTL, PanFlashLineMode, PanFlashEnhanceEnable);
// Init I-Cache
InitIcache(FLCTL, PanFlashLineMode);
@@ -90,32 +89,25 @@
*/
void SystemCoreClockUpdate(void)
{
-
-#ifdef FPGA_MODE
- //Fixed 32M System Clock on FPGA
- SystemCoreClock = FREQ_32MHZ;
-#else
uint32_t div = 0;
uint32_t freq_out = 0;
- div = (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_AHB_DIV_Msk) >> CLK_TOPCTL_AHB_DIV_Pos;
- if(div == 0)
- div = 1;
- else
- div += 1;
- if(CLK->CLK_TOP_CTRL_3V & CLK_SYS_SRCSEL_DPLL){
- freq_out = (CLK->DPLL_CTRL & CLK_DPLLCTL_FREQ_OUT_Msk);
- if(freq_out == CLK_DPLL_OUT_64M){
- SystemCoreClock = FREQ_64MHZ / div;
- }
- else{
- SystemCoreClock = FREQ_48MHZ / div;
- }
- }
- else{
- SystemCoreClock = FREQ_32MHZ / div;
- }
-#endif
+ div = (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_AHB_DIV_Msk) >> CLK_TOPCTL_AHB_DIV_Pos;
+ if (div == 0)
+ div = 1;
+ else
+ div += 1;
+
+ if (CLK->CLK_TOP_CTRL_3V & CLK_SYS_SRCSEL_DPLL) {
+ freq_out = (CLK->DPLL_CTRL & CLK_DPLLCTL_FREQ_OUT_Msk);
+ if(freq_out == CLK_DPLL_OUT_64M){
+ SystemCoreClock = FREQ_64MHZ / div;
+ } else {
+ SystemCoreClock = FREQ_48MHZ / div;
+ }
+ } else {
+ SystemCoreClock = FREQ_32MHZ / div;
+ }
}
static bool HwParamDataVerify(OTP_STRUCT_T *p_opt)
@@ -241,7 +233,7 @@
}
/*
- * Storing adc params related calibration. if adc symbol is not linked,
+ * Storing adc params related calibration. if adc symbol is not linked,
* this function would be handled as weak function.
*/
ADC_SetCalirationParams(otp);
@@ -268,8 +260,7 @@
}
-#if USE_ASSERT
-
+#if ASSERT_ON
/**
* @brief Assert Error Message
*
@@ -281,12 +272,11 @@
* @details The function prints the source file name and line number where
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
*/
-void AssertError(uint8_t * file, uint32_t line)
+void SYS_AssertError(uint8_t * file, uint32_t line, uint8_t * expr)
{
-
- SYS_DBG(" wrong parameters.\r\n", file, line);
+ LOG(true, "[SYS ASSERT] Assert Error! expr: \"%s\" (%s: %d)\n", expr, file, line);
/* Infinite loop */
- while(1) ;
+ while(1);
}
#endif
--
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