From 2c162b948f68bde8d17cb5e86d18a8972b5661f2 Mon Sep 17 00:00:00 2001
From: chen <15335560115@163.com>
Date: 星期二, 22 七月 2025 18:18:05 +0800
Subject: [PATCH] 修改传aoa信息逻辑为读取指令发送时并且为自身id才给，取消发送区域显示逻辑，将信号质量改为角度置信度
---
keil/include/drivers/mk_adc.c | 47 +++++++++++++++++++++++------------------------
1 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/keil/include/drivers/mk_adc.c b/keil/include/drivers/mk_adc.c
index e6c3dbf..6bccb99 100644
--- a/keil/include/drivers/mk_adc.c
+++ b/keil/include/drivers/mk_adc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
+ * Copyright (c) 2019-2025 Beijing Hanwei Innovation Technology Ltd. Co. and
* its subsidiaries and affiliates (collectly called MKSEMI).
*
* All rights reserved.
@@ -62,8 +62,7 @@
return DRV_ERROR;
}
- // check if ADC is using by HW or not
- if (adc_handle.base->STATUS & ADC_STATUS_BUSY_MSK)
+ if (adc_handle.state == ADC_STATE_BUSY)
{
return DRV_BUSY;
}
@@ -85,7 +84,7 @@
/* If the sampling rate setting exceeds the conversion rate threshold, the maximum sampling rate is used by default */
uint32_t rate = (adc_clk == ADC_CLK_LOW_FREQ) ? ((config->rate < ADC_CLK_L_MAX_SAMPLE_RATE) ? config->rate : ADC_CLK_L_MAX_SAMPLE_RATE)
- : (config->rate < ADC_CLK_H_MAX_SAMPLE_RATE ? config->rate : ADC_CLK_H_MAX_SAMPLE_RATE);
+ : (config->rate < ADC_CLK_H_MAX_SAMPLE_RATE ? config->rate : ADC_CLK_H_MAX_SAMPLE_RATE);
/* If the sample rate is set to 0, no frequency division */
uint16_t div = (uint16_t)((adc_clk / ((rate == 0) ? 1 : rate)) - 1);
@@ -104,6 +103,7 @@
/* If the external reference voltage driving capability is insufficient */
/* It is recommended to enable this configuration */
// val |= (9 << 1) | (1 << 4);
+ val |= (1 << 9) | (7 << 5) | (1 << 4);
}
REG_WRITE(0x4000062C, val);
@@ -125,8 +125,7 @@
int adc_close(void)
{
- // check if ADC is using by HW or not
- if ((adc_handle.base->STATUS & ADC_STATUS_BUSY_MSK) && (adc_handle.state != ADC_STATE_BUSY))
+ if (adc_handle.state == ADC_STATE_BUSY)
{
return DRV_BUSY;
}
@@ -173,17 +172,17 @@
// update state
switch (adc_handle.state)
{
- case ADC_STATE_READY:
- adc_handle.state = ADC_STATE_BUSY;
- break;
- case ADC_STATE_BUSY:
- int_unlock(lock);
- return DRV_BUSY;
- case ADC_STATE_RESET:
- case ADC_STATE_TIMEOUT:
- case ADC_STATE_ERROR:
- int_unlock(lock);
- return DRV_ERROR;
+ case ADC_STATE_READY:
+ adc_handle.state = ADC_STATE_BUSY;
+ break;
+ case ADC_STATE_BUSY:
+ int_unlock(lock);
+ return DRV_BUSY;
+ case ADC_STATE_RESET:
+ case ADC_STATE_TIMEOUT:
+ case ADC_STATE_ERROR:
+ int_unlock(lock);
+ return DRV_ERROR;
}
adc_handle.data = data;
@@ -209,6 +208,9 @@
dma_open(adc_handle.dma_ch, &adc_dma_cfg);
dma_transfer(adc_handle.dma_ch, (uint32_t *)&adc_handle.base->DATA, data, number, adc_dma_callback);
+
+ adc_handle.base->DMA_EN = ADC_DMA_EN_MSK;
+
// start conversion
adc_handle.base->CTRL2 = ADC_CTRL2_CONV_EN_MSK;
#endif
@@ -278,6 +280,8 @@
{
if (adc_handle.mode == ADC_MODE_CONTINUE)
{
+ adc_handle.base->DMA_EN &= ~ADC_DMA_EN_MSK;
+
// stop conversion
adc_handle.base->CTRL2 &= ~ADC_CTRL2_CONV_EN_MSK;
}
@@ -380,7 +384,7 @@
{
// enable ADC
struct ADC_CFG_T vs_adc_cfg;
- vs_adc_cfg.mode = ADC_MODE_SINGLE; /* Selected single conversion mode */
+ vs_adc_cfg.mode = ADC_MODE_CONTINUE; /* Selected single conversion mode */
vs_adc_cfg.clk_sel = ADC_CLK_HIGH; /* Selected 62.4M high speed clock */
vs_adc_cfg.vref_sel = ADC_SEL_VREF_INT; /* Using internal reference voltage (1.2V)*/
vs_adc_cfg.rate = 1000; /* ADC works at high frequency system clock, the maximum sampling rate is 2M */
@@ -405,17 +409,12 @@
adc_close();
}
-static void adc_continue_callback(void *data, uint32_t number)
-{
-
- LOG_INFO(TRACE_MODULE_APP, "Chip adc callback %d degree\r\n", data);
-}
int16_t battery_monitor_get(void)
{
#define NUM_SAMPLES (3)
uint32_t sample[NUM_SAMPLES];
- adc_get(&sample[0], NUM_SAMPLES, adc_continue_callback);
+ adc_get(&sample[0], NUM_SAMPLES, NULL);
int32_t sum = 0;
for (int i = 0; i < NUM_SAMPLES; i++)
--
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