From 2c162b948f68bde8d17cb5e86d18a8972b5661f2 Mon Sep 17 00:00:00 2001
From: chen <15335560115@163.com>
Date: 星期二, 22 七月 2025 18:18:05 +0800
Subject: [PATCH] 修改传aoa信息逻辑为读取指令发送时并且为自身id才给，取消发送区域显示逻辑，将信号质量改为角度置信度
---
keil/include/drivers/mk_flash.c | 188 ++++++++++++++++++++++++++++++++++++----------
1 files changed, 145 insertions(+), 43 deletions(-)
diff --git a/keil/include/drivers/mk_flash.c b/keil/include/drivers/mk_flash.c
index 950d46c..81d826a 100644
--- a/keil/include/drivers/mk_flash.c
+++ b/keil/include/drivers/mk_flash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
+ * Copyright (c) 2019-2025 Beijing Hanwei Innovation Technology Ltd. Co. and
* its subsidiaries and affiliates (collectly called MKSEMI).
*
* All rights reserved.
@@ -44,6 +44,11 @@
#include "mk_trace.h"
#include "mk_misc.h"
+#define CMP_MASK (1U << 6)
+#define DC_MASK (1U << 4)
+#define QE_MASK (1U << 1)
+#define SRP1_MASK (1U << 0)
+
#if FLASH_DMA_MODE_EN
static void flash_dma_callback(void *ch, uint32_t err_code);
static void flash_dma_write_nbytes_callback(void *ch, uint32_t err_code);
@@ -82,10 +87,38 @@
.is_open = 0,
#else
.is_open = 1, // Flash has been opened by default in XIP mode
+ .state = FLASH_STATE_READY,
#endif
},
};
+#if defined(XIP_EN)
+extern struct FLASH_CMD_T flash_cmd[FLASH_MAX_NUM][FLASH_OPCODE_NUM];
+struct FLASH_CMD_T flash_cmd[FLASH_MAX_NUM][FLASH_OPCODE_NUM] = {
+ {
+ // QUAD
+ //{false, FLASH_DATA_IN, FLASH_CMD_DATA_QUAD_DUAL, FLASH_CMD_OP_ADDR_3B, FLASH_SECTOR_SIZE, 1, 0x6B},
+ {false, FLASH_DATA_IN, FLASH_CMD_OP_SERIAL, FLASH_CMD_OP_ADDR_3B, FLASH_SECTOR_SIZE, 3, 0xEB},
+ {false, FLASH_DATA_OUT, FLASH_CMD_DATA_QUAD_DUAL, FLASH_CMD_OP_ADDR_3B, FLASH_PAGE_SIZE, 0, 0x32},
+ // DUAL
+ //{false, FLASH_DATA_IN, FLASH_CMD_DATA_QUAD_DUAL, FLASH_CMD_OP_ADDR_3B, FLASH_SECTOR_SIZE, 1, 0x3B},
+ //{false, FLASH_DATA_IN, FLASH_CMD_OP_SERIAL, FLASH_CMD_OP_ADDR_3B, FLASH_SECTOR_SIZE, 1, 0xBB},
+ //{false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ADDR_3B, FLASH_PAGE_SIZE, 0, 0x02},
+ // STD
+ //{false, FLASH_DATA_IN, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ADDR_3B, FLASH_SECTOR_SIZE, 0, 0x03},
+ //{false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ADDR_3B, FLASH_PAGE_SIZE, 0, 0x02},
+ {false, FLASH_DATA_IN, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 1, 0, 0x05},
+ {false, FLASH_DATA_IN, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 1, 0, 0x35},
+ {false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ADDR_3B, 0, 0, 0x20},
+ {false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ADDR_3B, 0, 0, 0xD8},
+ {false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 0, 0, 0x06},
+ {false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 2, 0, 0x01},
+ {false, FLASH_DATA_IN, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 3, 0, 0x9F},
+ {false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 0, 0, 0xB9}, // Deep power down
+ {false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 0, 0, 0xAB}, // Release from Deep power down
+ },
+};
+#else
static const struct FLASH_CMD_T flash_cmd[FLASH_MAX_NUM][FLASH_OPCODE_NUM] = {
{
// QUAD
@@ -110,8 +143,9 @@
{false, FLASH_DATA_OUT, FLASH_CMD_ALL_SERIAL, FLASH_CMD_OP_ONLY, 0, 0, 0xAB}, // Release from Deep power down
},
};
+#endif
-static void flash_wait_status(enum FLASH_DEV_T id, uint32_t mask, uint32_t status)
+static void RAM_FUNC flash_wait_status(enum FLASH_DEV_T id, uint32_t mask, uint32_t status)
{
uint32_t start = sys_timer_get();
while ((flash_handle[id].base->STATUS & mask) == status)
@@ -123,14 +157,14 @@
}
}
-static void flash_reset_cmd(enum FLASH_DEV_T id)
+static void RAM_FUNC flash_reset_cmd(enum FLASH_DEV_T id)
{
flash_handle[id].base->STATUS = FLASH_STATUS_RESET_MSK;
/* Wait for the RESET flag cleared by HW */
flash_wait_status(id, FLASH_STATUS_RESET_MSK, FLASH_STATUS_RESET_MSK);
}
-static void flash_write_cmd(enum FLASH_DEV_T id, enum FLASH_OPCODE_T opcode)
+static void RAM_FUNC flash_write_cmd(enum FLASH_DEV_T id, enum FLASH_OPCODE_T opcode)
{
/* Wait for the CMD and MCINT flag all be 0 */
flash_wait_status(id, FLASH_STATUS_MCINIT_MSK, FLASH_STATUS_MCINIT_MSK);
@@ -165,7 +199,7 @@
}
#if FLASH_WRITE_EN
-static void flash_write_variable_len_cmd(enum FLASH_DEV_T id, const uint32_t len)
+static void RAM_FUNC flash_write_variable_len_cmd(enum FLASH_DEV_T id, const uint32_t len)
{
/* Wait for the CMD and MCINT flag all be 0 */
flash_wait_status(id, FLASH_STATUS_MCINIT_MSK, FLASH_STATUS_MCINIT_MSK);
@@ -192,7 +226,7 @@
}
#endif
-static void flash_write_mem_cmd(enum FLASH_DEV_T id, enum FLASH_OPCODE_T opcode)
+static void RAM_FUNC flash_write_mem_cmd(enum FLASH_DEV_T id, enum FLASH_OPCODE_T opcode)
{
/* Wait for the CMD and MCINT flag all be 0 */
flash_wait_status(id, FLASH_STATUS_MCINIT_MSK, FLASH_STATUS_MCINIT_MSK);
@@ -203,7 +237,7 @@
FLASH_MCMD_OPCODE(flash_cmd[id][opcode].opcode);
}
-static uint8_t flash_read_status(enum FLASH_DEV_T id)
+static uint8_t RAM_FUNC flash_read_status(enum FLASH_DEV_T id)
{
flash_write_cmd(id, FLASH_OPCODE_GET_STATUS);
flash_wait_status(id, FLASH_STATUS_INTRQ_MSK, 0U);
@@ -219,7 +253,7 @@
return (val1);
}
-static void flash_wait_done(enum FLASH_DEV_T id, uint32_t timeout)
+static void RAM_FUNC flash_wait_done(enum FLASH_DEV_T id, uint32_t timeout)
{
uint32_t start = sys_timer_get();
/* Check WIP bit */
@@ -233,8 +267,51 @@
}
}
-static void flash_write_quad_mode(enum FLASH_DEV_T id, uint8_t qe_bit)
+static uint32_t flash_id_read(enum FLASH_DEV_T id)
{
+ uint32_t jedec_id = 0;
+
+ flash_write_cmd(id, FLASH_OPCODE_RDID);
+ flash_wait_status(id, FLASH_STATUS_INTRQ_MSK, 0U);
+
+ jedec_id = flash_handle[id].base->DATA;
+ jedec_id = (jedec_id << 8) + flash_handle[id].base->DATA;
+ jedec_id = (jedec_id << 8) + flash_handle[id].base->DATA;
+
+ // LOG_INFO(TRACE_MODULE_DRIVER, "jedec_id %x\r\n", jedec_id);
+ return jedec_id;
+}
+
+static void flash_write_quad_mode(enum FLASH_DEV_T id, uint8_t flash_type)
+{
+ uint8_t qe_bit = 0;
+ uint8_t s15_s8 = 0;
+
+ if (flash_type == 0)
+ {
+ // Check CMP/DC/QE/SRP1 bits(all non-volatile)
+ s15_s8 = flash_read_status1(id);
+ qe_bit = (s15_s8 & QE_MASK) ? 1 : 0;
+
+ // write quad mode if needed
+ if (((flash_handle[id].config.dual_mode == false) && (qe_bit == 0)) || ((flash_handle[id].config.dual_mode == true) && (qe_bit == 1)))
+ {
+ qe_bit = !qe_bit;
+ }
+ else if ((s15_s8 & (CMP_MASK | DC_MASK | SRP1_MASK)) != 0)
+ {
+ }
+ else
+ {
+ return;
+ }
+ }
+ else
+ {
+ // write quad mode anyway
+ qe_bit = !flash_handle[id].config.dual_mode;
+ }
+
// Write enable
flash_write_cmd(id, FLASH_OPCODE_WRITE_ENABLE);
@@ -242,7 +319,7 @@
flash_write_cmd(id, FLASH_OPCODE_WRITE_REGISTER);
// Enable Quad mode
- if (flash_handle[id].flash_type == 1)
+ if (flash_type == 1)
{
flash_handle[id].base->DATA = qe_bit ? 0x40 : 0x00;
flash_handle[id].base->DATA = 0x00;
@@ -328,13 +405,9 @@
flash_write_cmd(id, FLASH_OPCODE_RELEASE_POWER_DOWN);
delay_us(50);
- // Read Identification
- uint32_t jedec_id = 0;
- flash_write_cmd(id, FLASH_OPCODE_RDID);
- flash_wait_status(id, FLASH_STATUS_INTRQ_MSK, 0U);
-
- jedec_id = flash_handle[id].base->DATA;
- if (jedec_id == 0xC2)
+ // Update flash type
+ uint32_t jedec_id = flash_id_read(id);
+ if ((jedec_id & 0x00FF0000) == 0x00C20000)
{
flash_handle[id].flash_type = 1;
}
@@ -342,27 +415,9 @@
{
flash_handle[id].flash_type = 0;
}
- jedec_id = (jedec_id << 8) + flash_handle[id].base->DATA;
- jedec_id = (jedec_id << 8) + flash_handle[id].base->DATA;
- LOG_INFO(TRACE_MODULE_DRIVER, "jedec_id %x\r\n", jedec_id);
- // Check Quad enable bit, its a non-volatile bit
- uint8_t qe_bit = 0;
- if (flash_handle[id].flash_type == 1)
- {
- // write quad mode anyway
- flash_write_quad_mode(id, !flash_handle[id].config.dual_mode);
- }
- else
- {
- qe_bit = (flash_read_status1(id) >> 1) & 0x1;
-
- // write quad mode if needed
- if (((flash_handle[id].config.dual_mode == false) && (qe_bit == 0)) || ((flash_handle[id].config.dual_mode == true) && (qe_bit == 1)))
- {
- flash_write_quad_mode(id, !qe_bit);
- }
- }
+ // Set quad mode based on flash type
+ flash_write_quad_mode(id, flash_handle[id].flash_type);
if (flash_handle[id].promote_fclk == 1)
{
@@ -482,7 +537,11 @@
FLASH_CMD_FIELDFORM(FLASH_CMD_ALL_SERIAL) | FLASH_CMD_FRAMEFORM(FLASH_CMD_OP_ONLY) | FLASH_CMD_OPCODE(0xAB);
delay_us(30);
- // flash_write_cmd(id, FLASH_OPCODE_RELEASE_POWER_DOWN);
+
+#if BOR_EN
+ // enable BOR
+ SYSCON->BOD_BOR |= SYSCON_BOR_EN_MSK;
+#endif
}
}
@@ -494,8 +553,12 @@
flash_handle[id].base->CMD = FLASH_CMD_DATALEN(0) | FLASH_CMD_POLL(false) | FLASH_CMD_DOUT(FLASH_DATA_OUT) | FLASH_CMD_INTLEN(0) |
FLASH_CMD_FIELDFORM(FLASH_CMD_ALL_SERIAL) | FLASH_CMD_FRAMEFORM(FLASH_CMD_OP_ONLY) | FLASH_CMD_OPCODE(0xB9);
- // flash_write_cmd(id, FLASH_OPCODE_POWER_DOWN);
delay_us(15);
+
+#if BOR_EN
+ // disable BOR
+ SYSCON->BOD_BOR &= ~SYSCON_BOR_EN_MSK;
+#endif
}
}
@@ -505,7 +568,7 @@
#endif
#if FLASH_WRITE_EN
-static int flash_page_write_nbytes(enum FLASH_DEV_T id, uint32_t addr, const uint8_t *buf, uint32_t len)
+static int RAM_FUNC flash_page_write_nbytes(enum FLASH_DEV_T id, uint32_t addr, const uint8_t *buf, uint32_t len)
{
// Write enable
flash_write_cmd(id, FLASH_OPCODE_WRITE_ENABLE);
@@ -526,9 +589,9 @@
return DRV_OK;
}
-static int flash_page_write(enum FLASH_DEV_T id, uint32_t page, const uint8_t *buf)
+static int RAM_FUNC flash_page_write(enum FLASH_DEV_T id, uint32_t page, const uint8_t *buf)
{
- LOG_INFO(TRACE_MODULE_DRIVER, "flash_page_write %d\r\n", page);
+ // LOG_INFO(TRACE_MODULE_DRIVER, "flash_page_write %d\r\n", page);
// Write enable
flash_write_cmd(id, FLASH_OPCODE_WRITE_ENABLE);
@@ -559,6 +622,10 @@
{
return ret;
}
+
+#if defined(XIP_EN)
+ uint32_t lock = int_lock();
+#endif
// Reset the flash controller to switch to command mode
flash_reset_cmd(id);
@@ -596,6 +663,10 @@
flash_handle[id].state = FLASH_STATE_READY;
}
+#if defined(XIP_EN)
+ int_unlock(lock);
+#endif
+
return DRV_OK;
}
@@ -609,6 +680,10 @@
{
return ret;
}
+
+#if defined(XIP_EN)
+ uint32_t lock = int_lock();
+#endif
// Reset the flash controller to switch to command mode
flash_reset_cmd(id);
@@ -645,6 +720,11 @@
// update state
flash_handle[id].state = FLASH_STATE_READY;
}
+
+#if defined(XIP_EN)
+ int_unlock(lock);
+#endif
+
return DRV_OK;
}
@@ -764,6 +844,10 @@
flash_init_write_nbytes_cfg(id, start_addr, buf, len);
+#if defined(XIP_EN)
+ uint32_t lock = int_lock();
+#endif
+
// Reset the flash controller to switch to command mode
flash_reset_cmd(id);
if (flash_handle[id].config.dma_en)
@@ -867,6 +951,10 @@
flash_handle[id].state = FLASH_STATE_READY;
}
+#if defined(XIP_EN)
+ int_unlock(lock);
+#endif
+
return DRV_OK;
}
@@ -892,6 +980,10 @@
uint32_t offset_addr = start_addr - flash_handle[id].config.start_addr;
uint32_t page_start = offset_addr / flash_handle[id].config.page_size;
uint32_t page_end = (offset_addr + len) / flash_handle[id].config.page_size;
+
+#if defined(XIP_EN)
+ uint32_t lock = int_lock();
+#endif
// Reset the flash controller to switch to command mode
flash_reset_cmd(id);
@@ -946,6 +1038,11 @@
// update state
flash_handle[id].state = FLASH_STATE_READY;
}
+
+#if defined(XIP_EN)
+ int_unlock(lock);
+#endif
+
return DRV_OK;
}
#else
@@ -976,6 +1073,7 @@
return ret;
}
+#ifndef XIP_EN
// Reset the flash controller to switch to command mode
flash_reset_cmd(id);
@@ -1069,7 +1167,11 @@
// update state
flash_handle[id].state = FLASH_STATE_READY;
}
-
+#else
+ memcpy(buf, (uint8_t *)(start_addr), len);
+ // update state
+ flash_handle[id].state = FLASH_STATE_READY;
+#endif
return DRV_OK;
}
--
Gitblit v1.9.3