From fc78430a35be252a1cd5a29b5b66290a68cd9ca3 Mon Sep 17 00:00:00 2001
From: yincheng.zhong <634916154@qq.com>
Date: 星期二, 27 八月 2024 17:21:18 +0800
Subject: [PATCH] Merge branch '安邦测距手环' of http://47.108.70.204:60062/r/ChinaUWBProject into 安邦测距手环
---
keil/include/drivers/mk_clock.c | 88 ++++++++++++++++++++++----------------------
1 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/keil/include/drivers/mk_clock.c b/keil/include/drivers/mk_clock.c
index eaa51a8..470b8bc 100644
--- a/keil/include/drivers/mk_clock.c
+++ b/keil/include/drivers/mk_clock.c
@@ -172,17 +172,17 @@
switch (mux)
{
- case CLOCK_32K_CLK_SEL:
- clock_32K_clk_config(choice);
- break;
- case CLOCK_SYS_CLK_SEL:
- clock_sys_clk_config(choice);
- break;
- case CLOCK_WDT_CLK_SEL:
- clock_wdt_clk_config(choice);
- break;
- default:
- break;
+ case CLOCK_32K_CLK_SEL:
+ clock_32K_clk_config(choice);
+ break;
+ case CLOCK_SYS_CLK_SEL:
+ clock_sys_clk_config(choice);
+ break;
+ case CLOCK_WDT_CLK_SEL:
+ clock_wdt_clk_config(choice);
+ break;
+ default:
+ break;
}
}
@@ -190,21 +190,21 @@
{
switch (div_name)
{
- case CLOCK_AHB_DIV:
- SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_HCLK_DIV_MSK) | SYSCON_CLK_DIV_HCLK_DIV(div_value);
- break;
- case CLOCK_APB_DIV:
- SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_PCLK_DIV_MSK) | SYSCON_CLK_DIV_PCLK_DIV(div_value);
- break;
- case CLOCK_FLASH_CTRL_DIV:
- SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK) | SYSCON_CLK_DIV_FLASH_CTRL_DIV(div_value);
- break;
- case CLOCK_UART1_FDIV:
- SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART1_FDIV_MSK) | SYSCON_CLK_DIV_UART1_FDIV(div_value);
- break;
- case CLOCK_UART0_FDIV:
- SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART0_FDIV_MSK) | SYSCON_CLK_DIV_UART0_FDIV(div_value);
- break;
+ case CLOCK_AHB_DIV:
+ SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_HCLK_DIV_MSK) | SYSCON_CLK_DIV_HCLK_DIV(div_value);
+ break;
+ case CLOCK_APB_DIV:
+ SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_PCLK_DIV_MSK) | SYSCON_CLK_DIV_PCLK_DIV(div_value);
+ break;
+ case CLOCK_FLASH_CTRL_DIV:
+ SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK) | SYSCON_CLK_DIV_FLASH_CTRL_DIV(div_value);
+ break;
+ case CLOCK_UART1_FDIV:
+ SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART1_FDIV_MSK) | SYSCON_CLK_DIV_UART1_FDIV(div_value);
+ break;
+ case CLOCK_UART0_FDIV:
+ SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART0_FDIV_MSK) | SYSCON_CLK_DIV_UART0_FDIV(div_value);
+ break;
}
}
@@ -213,24 +213,24 @@
uint32_t freq = 0;
switch (clk_name)
{
- case CLOCK_SYS_CLK:
- freq = clock_get_sys_clk_freq();
- break;
- case CLOCK_AHB_CLK:
- freq = clock_get_ahb_clk_freq();
- break;
- case CLOCK_APB_CLK:
- freq = clock_get_apb_clk_freq();
- break;
- case CLOCK_WDT_CLK:
- freq = clock_get_wdt_clk_freq();
- break;
- case CLOCK_32K_CLK:
- freq = clock_get_32k_clk_freq();
- break;
- case CLOCK_FLASH_CLK:
- freq = clock_get_flash_clk_freq();
- break;
+ case CLOCK_SYS_CLK:
+ freq = clock_get_sys_clk_freq();
+ break;
+ case CLOCK_AHB_CLK:
+ freq = clock_get_ahb_clk_freq();
+ break;
+ case CLOCK_APB_CLK:
+ freq = clock_get_apb_clk_freq();
+ break;
+ case CLOCK_WDT_CLK:
+ freq = clock_get_wdt_clk_freq();
+ break;
+ case CLOCK_32K_CLK:
+ freq = clock_get_32k_clk_freq();
+ break;
+ case CLOCK_FLASH_CLK:
+ freq = clock_get_flash_clk_freq();
+ break;
}
return freq;
}
--
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