From fc78430a35be252a1cd5a29b5b66290a68cd9ca3 Mon Sep 17 00:00:00 2001
From: yincheng.zhong <634916154@qq.com>
Date: 星期二, 27 八月 2024 17:21:18 +0800
Subject: [PATCH] Merge branch '安邦测距手环' of http://47.108.70.204:60062/r/ChinaUWBProject into 安邦测距手环
---
keil/include/drivers/mk_uart.c | 262 ++++++++++++++++++++++++++--------------------------
1 files changed, 131 insertions(+), 131 deletions(-)
diff --git a/keil/include/drivers/mk_uart.c b/keil/include/drivers/mk_uart.c
index d101fe8..5b24f04 100644
--- a/keil/include/drivers/mk_uart.c
+++ b/keil/include/drivers/mk_uart.c
@@ -63,51 +63,51 @@
uint32_t SerialKeyPressed(uint8_t *key)//脜脨露脧脢媒戮脻脢脟路帽脢脮碌陆碌脛 MK8000脨脼赂脛
{
uint32_t status = uart_handle[1].base->STATUS;
- if (status & UART_STATUS_DR_MSK)
- {
+ if (status & UART_STATUS_DR_MSK)
+ {
//Serial0PutString("鲁脡鹿娄陆脫脢脮ing");
//uart_receive(UART_ID1,test_buf,10,NULL);
- *key = (uint8_t)uart_handle[1].base->RX_DATA;
+ *key = (uint8_t)uart_handle[1].base->RX_DATA;
//uart_rx_fifo_clear(UART_ID1);
- return 1;
- }
- else
- {
- return 0;
- }
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
}
void SerialPutChar(uint8_t c)
{
while (uart_handle[0].base->TX_FL)
- {
- }
-uart_send(UART_ID1, &c, 1, NULL);
+ {
+ }
+ uart_send(UART_ID1, &c, 1, NULL);
}
void Serial_PutString(uint8_t *s)
{
- while (*s != '\0')
- {
- SerialPutChar(*s);
- s++;
- }
+ while (*s != '\0')
+ {
+ SerialPutChar(*s);
+ s++;
+ }
}
void Serial0PutChar(uint8_t c)
- {//脜脨露脧脢媒戮脻禄潞麓忙脟酶脦陋驴脮录麓脡脧脪禄赂枚脳脰陆脷脢媒戮脻脪脩戮颅卤禄脣脥碌陆路垄脣脥录脛麓忙脝梅路垄脣脥鲁枚脠楼脕脣
- // wait TX FIFO empty
- while (uart_handle[0].base->TX_FL)
- {
- }
-uart_send(UART_ID0, &c, 1, NULL);
+{ //脜脨露脧脢媒戮脻禄潞麓忙脟酶脦陋驴脮录麓脡脧脪禄赂枚脳脰陆脷脢媒戮脻脪脩戮颅卤禄脣脥碌陆路垄脣脥录脛麓忙脝梅路垄脣脥鲁枚脠楼脕脣
+ // wait TX FIFO empty
+ while (uart_handle[0].base->TX_FL)
+ {
+ }
+ uart_send(UART_ID0, &c, 1, NULL);
}
void Serial0_PutString(uint8_t *s)
{
- while (*s != '\0')
- {
- Serial0PutChar(*s);
- s++;
- }
+ while (*s != '\0')
+ {
+ Serial0PutChar(*s);
+ s++;
+ }
}
static const struct UART_DIVISOR_T baud_table[] = {
{89, 6, 32}, // 1200
@@ -139,37 +139,37 @@
// update state
switch (uart_handle[id].state)
{
- case UART_STATE_READY:
- uart_handle[id].state = state;
- break;
- case UART_STATE_BUSY_RX:
- if (state == UART_STATE_BUSY_TX)
- {
- uart_handle[id].state = UART_STATE_BUSY_TX_RX;
- }
- else
- {
- ret = DRV_BUSY;
- }
- break;
- case UART_STATE_BUSY_TX:
- if (state == UART_STATE_BUSY_RX)
- {
- uart_handle[id].state = UART_STATE_BUSY_TX_RX;
- }
- else
- {
- ret = DRV_BUSY;
- }
- break;
- case UART_STATE_BUSY_TX_RX:
+ case UART_STATE_READY:
+ uart_handle[id].state = state;
+ break;
+ case UART_STATE_BUSY_RX:
+ if (state == UART_STATE_BUSY_TX)
+ {
+ uart_handle[id].state = UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
ret = DRV_BUSY;
- break;
- case UART_STATE_RESET:
- case UART_STATE_TIMEOUT:
- case UART_STATE_ERROR:
- ret = DRV_ERROR;
- break;
+ }
+ break;
+ case UART_STATE_BUSY_TX:
+ if (state == UART_STATE_BUSY_RX)
+ {
+ uart_handle[id].state = UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ ret = DRV_BUSY;
+ }
+ break;
+ case UART_STATE_BUSY_TX_RX:
+ ret = DRV_BUSY;
+ break;
+ case UART_STATE_RESET:
+ case UART_STATE_TIMEOUT:
+ case UART_STATE_ERROR:
+ ret = DRV_ERROR;
+ break;
}
int_unlock(lock);
@@ -784,105 +784,105 @@
switch (iid)
{
// modem status
- case 0x0:
- // clear int
- uart_handle[id].base->INTR_CLR = UART_INTR_CLR_MSR_INT_CLR_MSK;
- err_code = UART_ERR_MODEM | iid;
- break;
+ case 0x0:
+ // clear int
+ uart_handle[id].base->INTR_CLR = UART_INTR_CLR_MSR_INT_CLR_MSK;
+ err_code = UART_ERR_MODEM | iid;
+ break;
// no interrupt pending
- case 0x1:
- break;
+ case 0x1:
+ break;
// TX_DATA empty
- case 0x2:
- // clear int
- uart_handle[id].base->INTR_CLR = UART_INTR_CLR_THRE_INT_CLR_MSK;
- if ((uart_handle[id].state == UART_STATE_BUSY_TX) || (uart_handle[id].state == UART_STATE_BUSY_TX_RX))
+ case 0x2:
+ // clear int
+ uart_handle[id].base->INTR_CLR = UART_INTR_CLR_THRE_INT_CLR_MSK;
+ if ((uart_handle[id].state == UART_STATE_BUSY_TX) || (uart_handle[id].state == UART_STATE_BUSY_TX_RX))
+ {
+ if (uart_handle[id].tx_count == uart_handle[id].tx_size)
{
- if (uart_handle[id].tx_count == uart_handle[id].tx_size)
- {
- // TX done - disable interrupt
- uart_handle[id].base->INTR_EN &= ~UART_INTR_EN_ETBEI_MSK;
- usr_callback = uart_handle[id].tx_callback;
+ // TX done - disable interrupt
+ uart_handle[id].base->INTR_EN &= ~UART_INTR_EN_ETBEI_MSK;
+ usr_callback = uart_handle[id].tx_callback;
- // update state
- uart_state_clear(id, UART_STATE_BUSY_TX);
+ // update state
+ uart_state_clear(id, UART_STATE_BUSY_TX);
- uart_handle[id].tx_buff = NULL;
- uart_handle[id].tx_callback = NULL;
- uart_handle[id].tx_count = 0;
- uart_handle[id].tx_size = 0;
- }
- else
- {
- // TX continue - write data to FIFO
- while ((uart_handle[id].tx_count < uart_handle[id].tx_size) && (uart_handle[id].base->STATUS & UART_STATUS_TFNF_MSK))
- {
- uart_handle[id].base->TX_DATA = uart_handle[id].tx_buff[uart_handle[id].tx_count++];
- }
- }
+ uart_handle[id].tx_buff = NULL;
+ uart_handle[id].tx_callback = NULL;
+ uart_handle[id].tx_count = 0;
+ uart_handle[id].tx_size = 0;
}
else
{
- // should not get this interrupt in any other state
- ASSERT(0, "Uart %d state goes wrong %d", id, uart_handle[id].state);
+ // TX continue - write data to FIFO
+ while ((uart_handle[id].tx_count < uart_handle[id].tx_size) && (uart_handle[id].base->STATUS & UART_STATUS_TFNF_MSK))
+ {
+ uart_handle[id].base->TX_DATA = uart_handle[id].tx_buff[uart_handle[id].tx_count++];
+ }
}
- break;
+ }
+ else
+ {
+ // should not get this interrupt in any other state
+ ASSERT(0, "Uart %d state goes wrong %d", id, uart_handle[id].state);
+ }
+ break;
// timeout
- case 0xc:
+ case 0xc:
// No characters in or out of the RCVR FIFO during the last 4 character times and
// there is at least 1 character in it during this time
// received data available
- case 0x4:
- if ((uart_handle[id].state == UART_STATE_BUSY_RX) || (uart_handle[id].state == UART_STATE_BUSY_TX_RX))
+ case 0x4:
+ if ((uart_handle[id].state == UART_STATE_BUSY_RX) || (uart_handle[id].state == UART_STATE_BUSY_TX_RX))
+ {
+ // uint8_t len = uart_handle[id].base->RX_FL;
+ while ((uart_handle[id].rx_count < uart_handle[id].rx_size) && (uart_handle[id].base->STATUS & UART_STATUS_RFNE_MSK))
{
- // uint8_t len = uart_handle[id].base->RX_FL;
- while ((uart_handle[id].rx_count < uart_handle[id].rx_size) && (uart_handle[id].base->STATUS & UART_STATUS_RFNE_MSK))
- {
- uint8_t data = (uint8_t)uart_handle[id].base->RX_DATA;
- uart_handle[id].rx_buff[uart_handle[id].rx_count++] = data;
- }
-
- if (uart_handle[id].rx_count == uart_handle[id].rx_size)
- {
- // RX done - disable interrupts
- uart_handle[id].base->INTR_EN &= ~(UART_INTR_EN_ELSI_MSK | UART_INTR_EN_ERBFI_MSK);
- usr_callback = uart_handle[id].rx_callback;
-
- // update state
- uart_state_clear(id, UART_STATE_BUSY_RX);
-
- uart_handle[id].rx_buff = NULL;
- uart_handle[id].rx_callback = NULL;
- uart_handle[id].rx_count = 0;
- uart_handle[id].rx_size = 0;
- }
+ uint8_t data = (uint8_t)uart_handle[id].base->RX_DATA;
+ uart_handle[id].rx_buff[uart_handle[id].rx_count++] = data;
}
- else
+
+ if (uart_handle[id].rx_count == uart_handle[id].rx_size)
{
- // received unexpected data
+ // RX done - disable interrupts
+ uart_handle[id].base->INTR_EN &= ~(UART_INTR_EN_ELSI_MSK | UART_INTR_EN_ERBFI_MSK);
+ usr_callback = uart_handle[id].rx_callback;
+
+ // update state
+ uart_state_clear(id, UART_STATE_BUSY_RX);
+
+ uart_handle[id].rx_buff = NULL;
+ uart_handle[id].rx_callback = NULL;
+ uart_handle[id].rx_count = 0;
+ uart_handle[id].rx_size = 0;
}
- break;
+ }
+ else
+ {
+ // received unexpected data
+ }
+ break;
// receiver line status
- case 0x6:
- // clear int
- uart_handle[id].base->INTR_CLR = UART_INTR_CLR_LSR_INT_CLR_MSK;
- err_code = UART_ERR_LINE | iid;
- break;
+ case 0x6:
+ // clear int
+ uart_handle[id].base->INTR_CLR = UART_INTR_CLR_LSR_INT_CLR_MSK;
+ err_code = UART_ERR_LINE | iid;
+ break;
// busy detect
- case 0x7:
- // clear int
- uart_handle[id].base->INTR_CLR = UART_INTR_CLR_BUSY_INT_CLR_MSK;
- err_code = UART_ERR_BUSY | iid;
- break;
+ case 0x7:
+ // clear int
+ uart_handle[id].base->INTR_CLR = UART_INTR_CLR_BUSY_INT_CLR_MSK;
+ err_code = UART_ERR_BUSY | iid;
+ break;
- default:
- break;
+ default:
+ break;
}
#endif
}
--
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