From 7bd852c98c52c306e3628acedc33149ebee3cff6 Mon Sep 17 00:00:00 2001
From: guanjiao <sqrgj@163.com>
Date: 星期六, 12 五月 2018 23:35:39 +0800
Subject: [PATCH] format all the code
---
源码/核心板/Src/platform/lcd.c | 66
源码/核心板/Src/stm32f10x_it.c | 16
源码/核心板/Src/platform/port.c | 1062 +++++++-------
源码/核心板/Src/platform/deca_mutex.c | 34
源码/核心板/Src/platform/syscalls.c | 4
源码/核心板/Src/stm32f10x_it.h | 8
源码/核心板/Src/decadriver/deca_param_types.h | 9
源码/核心板/Src/decadriver/deca_regs.h | 68
源码/核心板/Src/platform/deca_spi.c | 64
源码/核心板/Src/decadriver/deca_device_api.h | 150 +-
源码/核心板/Src/main.c | 579 ++++---
源码/核心板/Src/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h | 202 +-
源码/核心板/Src/decadriver/deca_range_tables.c | 1072 +++++++-------
源码/核心板/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h | 16
源码/核心板/Src/decadriver/deca_params_init.c | 59
源码/核心板/Src/decadriver/deca_device.c | 881 ++++++------
源码/核心板/Src/platform/port.h | 8
17 files changed, 2,159 insertions(+), 2,139 deletions(-)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h"
index 0afac1b..f6169f6 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h"
@@ -1,6 +1,6 @@
/**
******************************************************************************
- * @file CAN/Networking/stm32f10x_conf.h
+ * @file CAN/Networking/stm32f10x_conf.h
* @author MCD Application Team
* @version V3.5.0
* @date 08-April-2011
@@ -17,7 +17,7 @@
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CONF_H
@@ -51,7 +51,7 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the
+/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
@@ -60,16 +60,16 @@
/**
* @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function which reports
- * the name of the source file and the source line number of the call
+ * @param expr: If expr is false, it calls assert_failed function which reports
+ * the name of the source file and the source line number of the call
* that failed. If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
#else
- #define assert_param(expr) ((void)0)
+#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* __STM32F10x_CONF_H */
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h"
index 162fa87..dcf8d08 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h"
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
- * @brief This file contains all the functions prototypes for the USART
+ * @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
* @attention
@@ -25,7 +25,7 @@
#define __STM32F10x_USART_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -37,73 +37,73 @@
/** @addtogroup USART
* @{
- */
+ */
/** @defgroup USART_Exported_Types
* @{
- */
+ */
-/**
- * @brief USART Init Structure definition
- */
-
+/**
+ * @brief USART Init Structure definition
+ */
+
typedef struct
{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
- uint16_t USART_Parity; /*!< Specifies the parity mode.
+ uint16_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
-
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
-/**
- * @brief USART Clock Init Structure definition
- */
-
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
typedef struct
{
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
- uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/**
* @}
- */
+ */
/** @defgroup USART_Exported_Constants
* @{
- */
-
+ */
+
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
@@ -118,23 +118,23 @@
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4))
-/** @defgroup USART_Word_Length
+/** @defgroup USART_Word_Length
* @{
- */
-
+ */
+
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
-
+
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
/**
* @}
- */
+ */
-/** @defgroup USART_Stop_Bits
+/** @defgroup USART_Stop_Bits
* @{
- */
-
+ */
+
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
@@ -145,36 +145,36 @@
((STOPBITS) == USART_StopBits_1_5))
/**
* @}
- */
+ */
-/** @defgroup USART_Parity
+/** @defgroup USART_Parity
* @{
- */
-
+ */
+
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
-#define USART_Parity_Odd ((uint16_t)0x0600)
+#define USART_Parity_Odd ((uint16_t)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/**
* @}
- */
+ */
-/** @defgroup USART_Mode
+/** @defgroup USART_Mode
* @{
- */
-
+ */
+
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
- */
+ */
-/** @defgroup USART_Hardware_Flow_Control
+/** @defgroup USART_Hardware_Flow_Control
* @{
- */
+ */
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
@@ -186,30 +186,30 @@
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/**
* @}
- */
+ */
-/** @defgroup USART_Clock
+/** @defgroup USART_Clock
* @{
- */
+ */
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/**
* @}
- */
+ */
-/** @defgroup USART_Clock_Polarity
+/** @defgroup USART_Clock_Polarity
* @{
*/
-
+
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/**
* @}
- */
+ */
/** @defgroup USART_Clock_Phase
* @{
@@ -233,12 +233,12 @@
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
- */
+ */
-/** @defgroup USART_Interrupt_definition
+/** @defgroup USART_Interrupt_definition
* @{
*/
-
+
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
@@ -265,7 +265,7 @@
* @}
*/
-/** @defgroup USART_DMA_Requests
+/** @defgroup USART_DMA_Requests
* @{
*/
@@ -275,7 +275,7 @@
/**
* @}
- */
+ */
/** @defgroup USART_WakeUp_methods
* @{
@@ -289,10 +289,10 @@
* @}
*/
-/** @defgroup USART_LIN_Break_Detection_Length
+/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
-
+
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
@@ -302,7 +302,7 @@
* @}
*/
-/** @defgroup USART_IrDA_Low_Power
+/** @defgroup USART_IrDA_Low_Power
* @{
*/
@@ -312,9 +312,9 @@
((MODE) == USART_IrDAMode_Normal))
/**
* @}
- */
+ */
-/** @defgroup USART_Flags
+/** @defgroup USART_Flags
* @{
*/
@@ -333,64 +333,64 @@
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-
+
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
- || ((USART_FLAG) != USART_FLAG_CTS))
+ || ((USART_FLAG) != USART_FLAG_CTS))
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/** @defgroup USART_Exported_Macros
* @{
- */
+ */
/**
* @}
- */
+ */
/** @defgroup USART_Exported_Functions
* @{
*/
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-void USART_SendBreak(USART_TypeDef* USARTx);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_DeInit(USART_TypeDef *USARTx);
+void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
+void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
+void USART_SendBreak(USART_TypeDef *USARTx);
+void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
@@ -399,14 +399,14 @@
#endif /* __STM32F10x_USART_H */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
index c9d0eea..93587d1 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
@@ -113,9 +113,9 @@
int dwt_initialise(uint16 config)
{
- uint8 plllockdetect = EC_CTRL_PLLLCK;
- uint16 otp_addr = 0;
- uint32 ldo_tune = 0;
+ uint8 plllockdetect = EC_CTRL_PLLLCK;
+ uint16 otp_addr = 0;
+ uint32 ldo_tune = 0;
dw1000local.dblbuffon = 0; // Double buffer mode off by default
dw1000local.prfIndex = 0; // 16MHz
@@ -135,23 +135,23 @@
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
- // Configure the CPLL lock detect
- dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
+ dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+ // Configure the CPLL lock detect
+ dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
- // Read OTP revision number
- otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
- dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte
+ // Read OTP revision number
+ otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
+ dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte
// Load LDO tune from OTP and kick it if there is a value actually programmed.
ldo_tune = _dwt_otpread(LDOTUNE_ADDRESS);
- if((ldo_tune & 0xFF) != 0)
- {
- uint8 ldok = OTP_SF_LDO_KICK;
- // Kick LDO tune
- dwt_writetodevice(OTP_IF_ID, OTP_SF, 1, &ldok); // Set load LDE kick bit
- dw1000local.sleep_mode |= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
- }
+ if((ldo_tune & 0xFF) != 0)
+ {
+ uint8 ldok = OTP_SF_LDO_KICK;
+ // Kick LDO tune
+ dwt_writetodevice(OTP_IF_ID, OTP_SF, 1, &ldok); // Set load LDE kick bit
+ dw1000local.sleep_mode |= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
+ }
// Load Part and Lot ID from OTP
dw1000local.partID = _dwt_otpread(PARTID_ADDRESS);
@@ -168,16 +168,16 @@
// Load leading edge detect code
if(config & DWT_LOADUCODE)
- {
+ {
_dwt_loaducodefromrom();
dw1000local.sleep_mode |= AON_WCFG_ONW_LLDE; // microcode must be loaded at wake-up
- }
- else // Should disable the LDERUN enable bit in 0x36, 0x4
- {
- uint16 rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1) ;
- rega &= 0xFDFF ; // Clear LDERUN bit
- dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1, rega) ;
- }
+ }
+ else // Should disable the LDERUN enable bit in 0x36, 0x4
+ {
+ uint16 rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET + 1) ;
+ rega &= 0xFDFF ; // Clear LDERUN bit
+ dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET + 1, rega) ;
+ }
_dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
@@ -201,7 +201,7 @@
*/
uint8 dwt_otprevision(void)
{
- return dw1000local.otprev ;
+ return dw1000local.otprev ;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -243,14 +243,14 @@
*/
void dwt_setGPIOdirection(uint32 gpioNum, uint32 direction)
{
- uint8 buf[GPIO_DIR_LEN];
- uint32 command = direction | gpioNum;
+ uint8 buf[GPIO_DIR_LEN];
+ uint32 command = direction | gpioNum;
- buf[0] = command & 0xff;
- buf[1] = (command >> 8) & 0xff;
- buf[2] = (command >> 16) & 0xff;
+ buf[0] = command & 0xff;
+ buf[1] = (command >> 8) & 0xff;
+ buf[2] = (command >> 16) & 0xff;
- dwt_writetodevice(GPIO_CTRL_ID, GPIO_DIR_OFFSET, GPIO_DIR_LEN, buf);
+ dwt_writetodevice(GPIO_CTRL_ID, GPIO_DIR_OFFSET, GPIO_DIR_LEN, buf);
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -268,14 +268,14 @@
*/
void dwt_setGPIOvalue(uint32 gpioNum, uint32 value)
{
- uint8 buf[GPIO_DOUT_LEN];
- uint32 command = value | gpioNum;
+ uint8 buf[GPIO_DOUT_LEN];
+ uint32 command = value | gpioNum;
- buf[0] = command & 0xff;
- buf[1] = (command >> 8) & 0xff;
- buf[2] = (command >> 16) & 0xff;
+ buf[0] = command & 0xff;
+ buf[1] = (command >> 8) & 0xff;
+ buf[2] = (command >> 16) & 0xff;
- dwt_writetodevice(GPIO_CTRL_ID, GPIO_DOUT_OFFSET, GPIO_DOUT_LEN, buf);
+ dwt_writetodevice(GPIO_CTRL_ID, GPIO_DOUT_OFFSET, GPIO_DOUT_LEN, buf);
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -323,7 +323,7 @@
*/
uint32 dwt_readdevid(void)
{
- return dwt_read32bitoffsetreg(DEV_ID_ID,0);
+ return dwt_read32bitoffsetreg(DEV_ID_ID, 0);
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -381,19 +381,19 @@
#ifdef DWT_API_ERROR_CHECK
if (config->dataRate > DWT_BR_6M8)
{
- return DWT_ERROR ;
+ return DWT_ERROR ;
}// validate datarate parameter
if ((config->prf > DWT_PRF_64M) || (config->prf < DWT_PRF_16M))
{
- return DWT_ERROR ; // validate Pulse Repetition Frequency
+ return DWT_ERROR ; // validate Pulse Repetition Frequency
}
if (config->rxPAC > DWT_PAC64)
{
- return DWT_ERROR ; // validate PAC size
+ return DWT_ERROR ; // validate PAC size
}
if ((chan < 1) || (chan > 7) || (6 == chan))
{
- return DWT_ERROR ; // validate channel number parameter
+ return DWT_ERROR ; // validate channel number parameter
}
// validate TX and TX pre-amble codes selections
@@ -416,8 +416,10 @@
case DWT_PLEN_512 :
case DWT_PLEN_256 :
case DWT_PLEN_128 :
- case DWT_PLEN_64 : break ; // all okay
- default : return DWT_ERROR ; // not a good preamble length parameter
+ case DWT_PLEN_64 :
+ break ; // all okay
+ default :
+ return DWT_ERROR ; // not a good preamble length parameter
}
if(config->phrMode > DWT_PHRMODE_EXT)
@@ -441,7 +443,7 @@
dw1000local.sysCFGreg |= (SYS_CFG_PHR_MODE_11 & (config->phrMode << 16)) ;
- dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
+ dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
// Set the lde_replicaCoeff
dwt_write16bitoffsetreg(LDE_IF_ID, LDE_REPC_OFFSET, reg16) ;
@@ -502,26 +504,26 @@
// Set (non-standard) user SFD for improved performance,
if(config->nsSFD)
{
- // Write non standard (DW) SFD length
- dwt_writetodevice(USR_SFD_ID,0x00,1,&dwnsSFDlen[config->dataRate]);
- nsSfd_result = 3 ;
- useDWnsSFD = 1 ;
+ // Write non standard (DW) SFD length
+ dwt_writetodevice(USR_SFD_ID, 0x00, 1, &dwnsSFDlen[config->dataRate]);
+ nsSfd_result = 3 ;
+ useDWnsSFD = 1 ;
}
regval = (CHAN_CTRL_TX_CHAN_MASK & (chan << CHAN_CTRL_TX_CHAN_SHIFT)) | // Transmit Channel
(CHAN_CTRL_RX_CHAN_MASK & (chan << CHAN_CTRL_RX_CHAN_SHIFT)) | // Receive Channel
(CHAN_CTRL_RXFPRF_MASK & (config->prf << CHAN_CTRL_RXFPRF_SHIFT)) | // RX PRF
- ((CHAN_CTRL_TNSSFD|CHAN_CTRL_RNSSFD) & (nsSfd_result << CHAN_CTRL_TNSSFD_SHIFT)) | // nsSFD enable RX&TX
+ ((CHAN_CTRL_TNSSFD | CHAN_CTRL_RNSSFD) & (nsSfd_result << CHAN_CTRL_TNSSFD_SHIFT)) | // nsSFD enable RX&TX
(CHAN_CTRL_DWSFD & (useDWnsSFD << CHAN_CTRL_DWSFD_SHIFT)) | // Use DW nsSFD
(CHAN_CTRL_TX_PCOD_MASK & (config->txCode << CHAN_CTRL_TX_PCOD_SHIFT)) | // TX Preamble Code
(CHAN_CTRL_RX_PCOD_MASK & (config->rxCode << CHAN_CTRL_RX_PCOD_SHIFT)) ; // RX Preamble Code
- dwt_write32bitreg(CHAN_CTRL_ID,regval) ;
+ dwt_write32bitreg(CHAN_CTRL_ID, regval) ;
// Set up TX Preamble Size and TX PRF
// Set up TX Ranging Bit and Data Rate
dw1000local.txFCTRL = (config->txPreambLength | config->prf) << 16;
dw1000local.txFCTRL |= (config->dataRate << TX_FCTRL_TXBR_SHFT) | TX_FCTRL_TR; // Always set ranging bit !!!
- dwt_write32bitoffsetreg(TX_FCTRL_ID,0,dw1000local.txFCTRL) ;
+ dwt_write32bitoffsetreg(TX_FCTRL_ID, 0, dw1000local.txFCTRL) ;
return DWT_SUCCESS ;
@@ -592,19 +594,19 @@
{
if (txFrameLength > 1023)
{
- return DWT_ERROR ;
+ return DWT_ERROR ;
}
}
else
{
if (txFrameLength > 127)
{
- return DWT_ERROR ;
+ return DWT_ERROR ;
}
}
if (txFrameLength < 2)
{
- return DWT_ERROR ;
+ return DWT_ERROR ;
}
#endif
@@ -613,7 +615,7 @@
return DWT_ERROR ;
}
// Write the data to the IC TX buffer, (-2 bytes for auto generated CRC)
- dwt_writetodevice( TX_BUFFER_ID, txBufferOffset, txFrameLength-2, txFrameBytes) ;
+ dwt_writetodevice( TX_BUFFER_ID, txBufferOffset, txFrameLength - 2, txFrameBytes) ;
return DWT_SUCCESS ;
@@ -643,26 +645,26 @@
{
if (txFrameLength > 1023)
{
- return DWT_ERROR ;
+ return DWT_ERROR ;
}
}
else
{
if (txFrameLength > 127)
{
- return DWT_ERROR ;
+ return DWT_ERROR ;
}
}
if (txFrameLength < 2)
{
- return DWT_ERROR ;
+ return DWT_ERROR ;
}
#endif
// Write the frame length to the TX frame control register
// dw1000local.txFCTRL has kept configured bit rate information
uint32 reg32 = dw1000local.txFCTRL | txFrameLength | (txBufferOffset << 22);
- dwt_write32bitoffsetreg(TX_FCTRL_ID,0,reg32) ;
+ dwt_write32bitoffsetreg(TX_FCTRL_ID, 0, reg32) ;
return DWT_SUCCESS ;
@@ -685,7 +687,7 @@
*/
void dwt_readrxdata(uint8 *buffer, uint16 length, uint16 rxBufferOffset)
{
- dwt_readfromdevice(RX_BUFFER_ID,rxBufferOffset,length,buffer) ;
+ dwt_readfromdevice(RX_BUFFER_ID, rxBufferOffset, length, buffer) ;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -707,7 +709,7 @@
// Force on the ACC clocks if we are sequenced
_dwt_enableclocks(READ_ACC_ON);
- dwt_readfromdevice(ACC_MEM_ID,accOffset,len,buffer) ;
+ dwt_readfromdevice(ACC_MEM_ID, accOffset, len, buffer) ;
_dwt_enableclocks(READ_ACC_OFF); // Revert clocks back
}
@@ -733,7 +735,7 @@
diagnostics->maxNoise = dwt_read16bitoffsetreg(LDE_IF_ID, LDE_THRESH_OFFSET);
// Read all 8 bytes in one SPI transaction
- dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8*)&diagnostics->stdNoise);
+ dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8 *)&diagnostics->stdNoise);
//diagnostics->stdNoise = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x0) ;
//diagnostics->firstPathAmp2 = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x2) ;
//diagnostics->firstPathAmp3 = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x4) ;
@@ -760,7 +762,7 @@
*
* no return value
*/
-void dwt_readtxtimestamp(uint8 * timestamp)
+void dwt_readtxtimestamp(uint8 *timestamp)
{
dwt_readfromdevice(TX_TIME_ID, 0, TX_TIME_TX_STAMP_LEN, timestamp) ; // Read bytes directly into buffer
}
@@ -809,7 +811,7 @@
*
* no return value
*/
-void dwt_readrxtimestamp(uint8 * timestamp)
+void dwt_readrxtimestamp(uint8 *timestamp)
{
dwt_readfromdevice(RX_TIME_ID, 0, RX_TIME_RX_STAMP_LEN, timestamp) ; // Get the adjusted time of arrival
}
@@ -875,7 +877,7 @@
*
* no return value
*/
-void dwt_readsystime(uint8 * timestamp)
+void dwt_readsystime(uint8 *timestamp)
{
dwt_readfromdevice(SYS_TIME_ID, 0, SYS_TIME_LEN, timestamp) ;
}
@@ -933,7 +935,7 @@
{
return DWT_ERROR ; // Index is limited to 15-bits.
}
- if ((index + length)> 0x7FFF)
+ if ((index + length) > 0x7FFF)
{
return DWT_ERROR ; // Sub-addressable area is limited to 15-bits.
}
@@ -952,7 +954,7 @@
}
// Write it to the SPI
- return writetospi(cnt,header,length,buffer);
+ return writetospi(cnt, header, length, buffer);
} // end dwt_writetodevice()
@@ -1008,7 +1010,7 @@
{
return DWT_ERROR ; // Index is limited to 15-bits.
}
- if ((index + length)> 0x7FFF)
+ if ((index + length) > 0x7FFF)
{
return DWT_ERROR ; // Sub-addressable area is limited to 15-bits.
}
@@ -1046,13 +1048,13 @@
*
* returns 32 bit register value (success), or DWT_ERROR for error
*/
-uint32 dwt_read32bitoffsetreg(int regFileID,int regOffset)
+uint32 dwt_read32bitoffsetreg(int regFileID, int regOffset)
{
uint32 regval = DWT_ERROR ;
int j ;
uint8 buffer[4] ;
- int result = dwt_readfromdevice(regFileID,regOffset,4,buffer); // Read 4 bytes (32-bits) register into buffer
+ int result = dwt_readfromdevice(regFileID, regOffset, 4, buffer); // Read 4 bytes (32-bits) register into buffer
if(result == DWT_SUCCESS)
{
@@ -1078,12 +1080,12 @@
*
* returns 16 bit register value (success), or DWT_ERROR for error
*/
-uint16 dwt_read16bitoffsetreg(int regFileID,int regOffset)
+uint16 dwt_read16bitoffsetreg(int regFileID, int regOffset)
{
uint16 regval = DWT_ERROR ;
uint8 buffer[2] ;
- int result = dwt_readfromdevice(regFileID,regOffset,2,buffer); // Read 2 bytes (16-bits) register into buffer
+ int result = dwt_readfromdevice(regFileID, regOffset, 2, buffer); // Read 2 bytes (16-bits) register into buffer
if(result == DWT_SUCCESS)
{
@@ -1107,7 +1109,7 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_write16bitoffsetreg(int regFileID,int regOffset,uint16 regval)
+int dwt_write16bitoffsetreg(int regFileID, int regOffset, uint16 regval)
{
int reg;
uint8 buffer[2] ;
@@ -1115,7 +1117,7 @@
buffer[0] = regval & 0xFF;
buffer[1] = regval >> 8 ;
- reg = dwt_writetodevice(regFileID,regOffset,2,buffer);
+ reg = dwt_writetodevice(regFileID, regOffset, 2, buffer);
return reg;
@@ -1135,7 +1137,7 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_write32bitoffsetreg(int regFileID,int regOffset,uint32 regval)
+int dwt_write32bitoffsetreg(int regFileID, int regOffset, uint32 regval)
{
int j ;
int reg;
@@ -1147,7 +1149,7 @@
regval >>= 8 ;
}
- reg = dwt_writetodevice(regFileID,regOffset,4,buffer);
+ reg = dwt_writetodevice(regFileID, regOffset, 4, buffer);
return reg;
@@ -1189,7 +1191,7 @@
}
dw1000local.sysCFGreg = sysconfig ;
- dwt_write32bitreg(SYS_CFG_ID,sysconfig) ;
+ dwt_write32bitreg(SYS_CFG_ID, sysconfig) ;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -1282,7 +1284,7 @@
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: Set system clock to XTAL - this is necessary to make sure the values read by _dwt_otpread are reliable
- for(i=0; i<length; i++)
+ for(i = 0; i < length; i++)
{
array[i] = _dwt_otpread(address + i) ;
}
@@ -1309,20 +1311,20 @@
uint8 buf[4];
uint32 ret_data;
- buf[1] = (address>>8) & 0xff;
+ buf[1] = (address >> 8) & 0xff;
buf[0] = address & 0xff;
// Write the address
- dwt_writetodevice(OTP_IF_ID,OTP_ADDR,2,buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_ADDR, 2, buf);
// Assert OTP Read (self clearing)
buf[0] = 0x03; // 0x03 for manual drive of OTP_READ
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL,1,buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, buf);
buf[0] = 0x00; // Bit0 is not autoclearing, so clear it (Bit 1 is but we clear it anyway).
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL,1,buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, buf);
// Read read data, available 40ns after rising edge of OTP_READ
- ret_data=dwt_read32bitoffsetreg(OTP_IF_ID,OTP_RDAT);
+ ret_data = dwt_read32bitoffsetreg(OTP_IF_ID, OTP_RDAT);
// Return the 32bit of read data
return (ret_data);
@@ -1352,151 +1354,152 @@
{
uint8 rd_buf[4];
uint8 wr_buf[4];
- uint32 mra=0,mrb=0,mr=0;
+ uint32 mra = 0, mrb = 0, mr = 0;
//printf("OTP SET MR: Setting MR,MRa,MRb for mode %2x\n",mode);
// PROGRAMME MRA
// Set MRA, MODE_SEL
wr_buf[0] = 0x03;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
// Load data
- switch(mode&0x0f) {
+ switch(mode & 0x0f)
+ {
case 0x0 :
- mr =0x0000;
- mra=0x0000;
- mrb=0x0000;
+ mr = 0x0000;
+ mra = 0x0000;
+ mrb = 0x0000;
break;
case 0x1 :
- mr =0x1024;
- mra=0x9220; // Enable CPP mon
- mrb=0x000e;
+ mr = 0x1024;
+ mra = 0x9220; // Enable CPP mon
+ mrb = 0x000e;
break;
case 0x2 :
- mr =0x1824;
- mra=0x9220;
- mrb=0x0003;
+ mr = 0x1824;
+ mra = 0x9220;
+ mrb = 0x0003;
break;
case 0x3 :
- mr =0x1824;
- mra=0x9220;
- mrb=0x004e;
+ mr = 0x1824;
+ mra = 0x9220;
+ mrb = 0x004e;
break;
case 0x4 :
- mr =0x0000;
- mra=0x0000;
- mrb=0x0003;
+ mr = 0x0000;
+ mra = 0x0000;
+ mrb = 0x0003;
break;
case 0x5 :
- mr =0x0024;
- mra=0x0000;
- mrb=0x0003;
+ mr = 0x0024;
+ mra = 0x0000;
+ mrb = 0x0003;
break;
default :
- // printf("OTP SET MR: ERROR : Invalid mode selected\n",mode);
+ // printf("OTP SET MR: ERROR : Invalid mode selected\n",mode);
return DWT_ERROR;
}
wr_buf[0] = mra & 0x00ff;
- wr_buf[1] = (mra & 0xff00)>>8;
- dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
+ wr_buf[1] = (mra & 0xff00) >> 8;
+ dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 2, wr_buf);
// Set WRITE_MR
wr_buf[0] = 0x08;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
// Wait?
// Set Clear Mode sel
wr_buf[0] = 0x02;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
// Set AUX update, write MR
wr_buf[0] = 0x88;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
// Clear write MR
wr_buf[0] = 0x80;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
// Clear AUX update
wr_buf[0] = 0x00;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
///////////////////////////////////////////
// PROGRAM MRB
// Set SLOW, MRB, MODE_SEL
wr_buf[0] = 0x05;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
wr_buf[0] = mrb & 0x00ff;
- wr_buf[1] = (mrb & 0xff00)>>8;
- dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
+ wr_buf[1] = (mrb & 0xff00) >> 8;
+ dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 2, wr_buf);
// Set WRITE_MR
wr_buf[0] = 0x08;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
// Wait?
// Set Clear Mode sel
wr_buf[0] = 0x04;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
// Set AUX update, write MR
wr_buf[0] = 0x88;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
// Clear write MR
wr_buf[0] = 0x80;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
// Clear AUX update
wr_buf[0] = 0x00;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
///////////////////////////////////////////
// PROGRAM MR
// Set SLOW, MODE_SEL
wr_buf[0] = 0x01;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
// Load data
wr_buf[0] = mr & 0x00ff;
- wr_buf[1] = (mr & 0xff00)>>8;
- dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
+ wr_buf[1] = (mr & 0xff00) >> 8;
+ dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 2, wr_buf);
// Set WRITE_MR
wr_buf[0] = 0x08;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
// Wait?
deca_sleep(10);
// Set Clear Mode sel
wr_buf[0] = 0x00;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
// Read confirm mode writes.
// Set man override, MRA_SEL
wr_buf[0] = OTP_CTRL_OTPRDEN;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
wr_buf[0] = 0x02;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
// MRB_SEL
wr_buf[0] = 0x04;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
deca_sleep(100);
// Clear mode sel
wr_buf[0] = 0x00;
- dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
// Clear MAN_OVERRIDE
wr_buf[0] = 0x00;
- dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
+ dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
deca_sleep(10);
- if (((mode&0x0f) == 0x1)||((mode&0x0f) == 0x2))
- {
+ if (((mode & 0x0f) == 0x1) || ((mode & 0x0f) == 0x2))
+ {
// Read status register
- dwt_readfromdevice(OTP_IF_ID, OTP_STAT,1,rd_buf);
+ dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
}
return DWT_SUCCESS;
@@ -1527,19 +1530,19 @@
if((rd_buf[0] & 0x02) != 0x02)
{
-// printf("OTP PROG 32: ERROR VPP NOT OK, programming will fail. Are MR/MRA/MRB set?\n");
+ // printf("OTP PROG 32: ERROR VPP NOT OK, programming will fail. Are MR/MRA/MRB set?\n");
return DWT_ERROR;
}
// Write the data
- wr_buf[3] = (data>>24) & 0xff;
- wr_buf[2] = (data>>16) & 0xff;
- wr_buf[1] = (data>>8) & 0xff;
+ wr_buf[3] = (data >> 24) & 0xff;
+ wr_buf[2] = (data >> 16) & 0xff;
+ wr_buf[1] = (data >> 8) & 0xff;
wr_buf[0] = data & 0xff;
dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 4, wr_buf);
// Write the address [10:0]
- wr_buf[1] = (address>>8) & 0x07;
+ wr_buf[1] = (address >> 8) & 0x07;
wr_buf[0] = address & 0xff;
dwt_writetodevice(OTP_IF_ID, OTP_ADDR, 2, wr_buf);
@@ -1602,7 +1605,7 @@
break;
}
retry++;
- if(retry==5)
+ if(retry == 5)
{
break;
}
@@ -1638,9 +1641,9 @@
uint8 buf[1];
buf[0] = 0x04;
- dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
buf[0] = 0x00;
- dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -1660,9 +1663,9 @@
uint8 buf[1];
buf[0] = 0x00;
- dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
buf[0] = 0x02;
- dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -1702,7 +1705,7 @@
uint8 buf[2];
buf[0] = 0x01;
- dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
+ dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);
buf[0] = 0;
dwt_writetodevice(AON_ID, AON_CFG0_OFFSET, 1, buf); // To make sure we don't accidentaly go to sleep
@@ -1715,7 +1718,7 @@
// Set new value
buf[0] = sleepcnt & 0xFF;
buf[1] = (sleepcnt >> 8) & 0xFF;
- dwt_writetodevice(AON_ID, (AON_CFG0_OFFSET+2) , 2, buf);
+ dwt_writetodevice(AON_ID, (AON_CFG0_OFFSET + 2) , 2, buf);
_dwt_aonconfigupload();
// Enable the sleep counter
@@ -1724,7 +1727,7 @@
_dwt_aonconfigupload();
buf[0] = 0x00;
- dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
+ dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);
}
@@ -1757,48 +1760,48 @@
_dwt_aonconfigupload();
buf[0] = 0x01;
- dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
+ dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);
deca_sleep(1);
// Read the number of XTAL/2 cycles one lposc cycle took.
// Set up address
buf[0] = 118;
- dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1,buf);
+ dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1, buf);
// Enable manual override
buf[0] = 0x80; // OVR EN
- dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
// Read confirm data that was written
buf[0] = 0x88; // OVR EN, OVR_RD
- dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
// Read back byte from AON
- dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1,buf);
+ dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1, buf);
result = buf[0];
result = result << 8;
// Set up address
buf[0] = 117;
- dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1,buf);
+ dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1, buf);
// Enable manual override
buf[0] = 0x80; // OVR EN
- dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
// Read confirm data that was written
buf[0] = 0x88; // OVR EN, OVR_RD
- dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
// Read back byte from AON
- dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1,buf);
+ dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1, buf);
result |= buf[0];
buf[0] = 0x00; // Disable OVR EN
- dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
+ dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
buf[0] = 0x00;
- dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
+ dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);
// Returns the number of XTAL/2 cycles per one LP OSC cycle
// This can be converted into LP OSC frequency by 19.2 MHz/result
@@ -2045,7 +2048,7 @@
dw1000local.sysCFGreg |= SYS_CFG_DIS_STXP ;
}
- dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
+ dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
}
@@ -2069,7 +2072,7 @@
dwt_write16bitoffsetreg(ACK_RESP_T_ID, 0x2, (responseDelayTime << 8) ) ; //in symbols
// Enable auto ACK
dw1000local.sysCFGreg |= SYS_CFG_AUTOACK;
- dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
+ dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -2099,7 +2102,7 @@
dw1000local.dblbuffon = 0;
}
- dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
+ dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -2116,12 +2119,12 @@
*/
void dwt_setautorxreenable(int enable)
{
- uint8 byte = 0;
+ uint8 byte = 0;
if(enable)
{
// Enable auto re-enable of the receiver
- dw1000local.sysCFGreg |= SYS_CFG_RXAUTR;
+ dw1000local.sysCFGreg |= SYS_CFG_RXAUTR;
}
else
{
@@ -2129,7 +2132,7 @@
dw1000local.sysCFGreg &= ~SYS_CFG_RXAUTR;
}
- byte = dw1000local.sysCFGreg >> 24;
+ byte = dw1000local.sysCFGreg >> 24;
dwt_writetodevice(SYS_CFG_ID, 3, 1, &byte) ;
}
@@ -2192,9 +2195,9 @@
{
uint8 temp;
- dwt_readfromdevice(SYS_STATUS_ID, 0, 1, &temp);
+ dwt_readfromdevice(SYS_STATUS_ID, 0, 1, &temp);
- return (temp & 0x1) ;
+ return (temp & 0x1) ;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -2219,9 +2222,9 @@
uint32 clear = 0; // Will clear any events seen
dw1000local.cdata.event = 0;
- dw1000local.cdata.dblbuff = dw1000local.dblbuffon ;
+ dw1000local.cdata.dblbuff = dw1000local.dblbuffon ;
- status = dw1000local.cdata.status = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register low 32bits
+ status = dw1000local.cdata.status = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register low 32bits
//NOTES:
//1. TX Event - if DWT_INT_TFRS is enabled, then when the frame has completed transmission the interrupt will be triggered.
@@ -2234,81 +2237,81 @@
// This function will clear the rx event and call the dwt_rxcallback function, notifying the application that ACK req is set.
// If using auto-ACK, the AAT indicates that ACK frame transmission is in progress. Once the ACK has been sent the TXFRS bit will be set and TX event triggered.
// If the auto-ACK is not enabled, the application can format/configure and start transmission of its own ACK frame.
- //
+ //
- // Fix for bug 622 - LDE done flag gets latched on a bad frame
- if((status & SYS_STATUS_LDEDONE) && (dw1000local.dblbuffon == 0))
- {
- if((status & (SYS_STATUS_LDEDONE | SYS_STATUS_RXPHD | SYS_STATUS_RXSFDD)) != (SYS_STATUS_LDEDONE | SYS_STATUS_RXPHD | SYS_STATUS_RXSFDD))
- {
+ // Fix for bug 622 - LDE done flag gets latched on a bad frame
+ if((status & SYS_STATUS_LDEDONE) && (dw1000local.dblbuffon == 0))
+ {
+ if((status & (SYS_STATUS_LDEDONE | SYS_STATUS_RXPHD | SYS_STATUS_RXSFDD)) != (SYS_STATUS_LDEDONE | SYS_STATUS_RXPHD | SYS_STATUS_RXSFDD))
+ {
- // Got LDE done but other flags SFD and PHR are clear - this is a bad frame - reset the transceiver
- dwt_forcetrxoff(); //this will clear all events
+ // Got LDE done but other flags SFD and PHR are clear - this is a bad frame - reset the transceiver
+ dwt_forcetrxoff(); //this will clear all events
- dwt_rxreset();
- // Leave any TX events for processing (e.g. if we TX a frame, and then enable RX,
- // We can get into here before the TX frame done has been processed, when we are polling (i.e. slow to process the TX)
- status &= SYS_STATUS_ALL_TX;
- // Re-enable the receiver - if auto RX re-enable set
- if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR)
- {
- dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
- }
- else
- {
- dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
+ dwt_rxreset();
+ // Leave any TX events for processing (e.g. if we TX a frame, and then enable RX,
+ // We can get into here before the TX frame done has been processed, when we are polling (i.e. slow to process the TX)
+ status &= SYS_STATUS_ALL_TX;
+ // Re-enable the receiver - if auto RX re-enable set
+ if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR)
+ {
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
+ }
+ else
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
- if(dw1000local.dwt_rxcallback != NULL)
- dw1000local.dwt_rxcallback(&dw1000local.cdata);
- }
- }
- }
+ if(dw1000local.dwt_rxcallback != NULL)
+ dw1000local.dwt_rxcallback(&dw1000local.cdata);
+ }
+ }
+ }
//
// 1st check for RX frame received or RX timeout and if so call the rx callback function
//
if(status & SYS_STATUS_RXFCG) // Receiver FCS Good
- {
- if(status & SYS_STATUS_LDEDONE) // LDE done/finished
- {
- // Bug 634 - overrun overwrites the frame info data... so both frames should be discarded
- // Read frame info and other registers and check for overflow again
- // If overflow set then discard both frames...
+ {
+ if(status & SYS_STATUS_LDEDONE) // LDE done/finished
+ {
+ // Bug 634 - overrun overwrites the frame info data... so both frames should be discarded
+ // Read frame info and other registers and check for overflow again
+ // If overflow set then discard both frames...
- uint16 len = 0;
+ uint16 len = 0;
- if (status & SYS_STATUS_RXOVRR) // NOTE when overrun both HS and RS pointers point to the same buffer
- {
- // When the overrun happens the frame info data of the buffer A (which contains the older frame e.g. seq. num = x)
- // will be corrupted with the latest frame (seq. num = x + 2) data, both the host and IC are pointing to buffer A
- // We are going to discard this frame - turn off transceiver and reset receiver
- dwt_forcetrxoff();
+ if (status & SYS_STATUS_RXOVRR) // NOTE when overrun both HS and RS pointers point to the same buffer
+ {
+ // When the overrun happens the frame info data of the buffer A (which contains the older frame e.g. seq. num = x)
+ // will be corrupted with the latest frame (seq. num = x + 2) data, both the host and IC are pointing to buffer A
+ // We are going to discard this frame - turn off transceiver and reset receiver
+ dwt_forcetrxoff();
- dwt_rxreset();
+ dwt_rxreset();
- if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here (ignore error)
- {
- dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
- }
- else // The RX will be re-enabled by the application, report an error
- {
- dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
+ if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here (ignore error)
+ {
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
+ }
+ else // The RX will be re-enabled by the application, report an error
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
- if(dw1000local.dwt_rxcallback != NULL)
- {
- dw1000local.dwt_rxcallback(&dw1000local.cdata);
- }
- }
+ if(dw1000local.dwt_rxcallback != NULL)
+ {
+ dw1000local.dwt_rxcallback(&dw1000local.cdata);
+ }
+ }
- return;
- }
- else // No overrun condition - proceed to process the frame
- {
+ return;
+ }
+ else // No overrun condition - proceed to process the frame
+ {
len = dwt_read16bitoffsetreg(RX_FINFO_ID, 0) & 0x3FF;
- dwt_readfromdevice(RX_BUFFER_ID,0,2,dw1000local.cdata.fctrl) ;
- if (dw1000local.longFrames==0)
+ dwt_readfromdevice(RX_BUFFER_ID, 0, 2, dw1000local.cdata.fctrl) ;
+ if (dw1000local.longFrames == 0)
{
len &= 0x7F ;
}
@@ -2318,8 +2321,8 @@
// Bug 627 workaround - clear the AAT bit if the ACK request bit in the FC is not set
if((status & SYS_STATUS_AAT) // AAT bit is set (ACK has been requested)
- && (((dw1000local.cdata.fctrl[0] & 0x20) == 0) || (dw1000local.cdata.fctrl[0] == 0x02)) // But the data frame has it clear or it is an ACK frame
- )
+ && (((dw1000local.cdata.fctrl[0] & 0x20) == 0) || (dw1000local.cdata.fctrl[0] == 0x02)) // But the data frame has it clear or it is an ACK frame
+ )
{
clear |= SYS_STATUS_AAT ;
dw1000local.cdata.aatset = 0 ; // ACK request is not set
@@ -2336,7 +2339,7 @@
{
// Clear all receive status bits (as we are finished with this receive event)
clear |= status & SYS_STATUS_ALL_RX_GOOD ;
- dwt_write32bitreg(SYS_STATUS_ID,clear) ; // Write status register to clear event bits we have seen
+ dwt_write32bitreg(SYS_STATUS_ID, clear) ; // Write status register to clear event bits we have seen
// NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
// New events can trigger and give rise to new interrupts
@@ -2356,17 +2359,17 @@
dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &buff);
// If ICRBP is equal to HSRBP this means we've received another frame (both buffers have frames)
if((buff & (SYS_STATUS_ICRBP >> 24)) == // IC side Receive Buffer Pointer
- ((buff & (SYS_STATUS_HSRBP >> 24)) << 1)) // Host Side Receive Buffer Pointer
+ ((buff & (SYS_STATUS_HSRBP >> 24)) << 1)) // Host Side Receive Buffer Pointer
{
// Clear all receive status bits (as we are finished with this receive event)
clear |= status & SYS_STATUS_ALL_DBLBUFF;
- dwt_write32bitreg(SYS_STATUS_ID,clear); // Write status register to clear event bits we have seen
+ dwt_write32bitreg(SYS_STATUS_ID, clear); // Write status register to clear event bits we have seen
}
// If they are not aligned then there is a new frame in the other buffer, so we just need to toggle...
if((dw1000local.sysCFGreg & SYS_CFG_RXAUTR) == 0) // Double buffer is on but no auto RX re-enable RX
{
- dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
}
// Call the RX call-back function to process the RX event
@@ -2391,122 +2394,122 @@
if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here
{
- dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
}
}
} // end of else double buffer
- }// end of no overrun
- } // If LDE_DONE is set (this means we have both SYS_STATUS_RXFCG and SYS_STATUS_LDEDONE)
- else // No LDE_DONE ?
- {
- //printf("NO LDE done or LDE error\n");
- if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
- {
- dwt_forcetrxoff();
- }
- dwt_rxreset(); // Reset the RX
- dw1000local.wait4resp = 0;
- dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
- if(dw1000local.dwt_rxcallback != NULL)
- {
- dw1000local.dwt_rxcallback(&dw1000local.cdata);
- }
- }
- } // end if CRC is good
- else
- //
- // Check for TX frame sent event and signal to upper layer.
- //
- if (status & SYS_STATUS_TXFRS) // Transmit Frame Sent
- {
- clear |= SYS_STATUS_ALL_TX; //clear TX event bits
- dwt_write32bitreg(SYS_STATUS_ID,clear); // Write status register to clear event bits we have seen
- // NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
- // New events can trigger and give rise to new interrupts
- if(dw1000local.cdata.aatset)
+ }// end of no overrun
+ } // If LDE_DONE is set (this means we have both SYS_STATUS_RXFCG and SYS_STATUS_LDEDONE)
+ else // No LDE_DONE ?
{
- dw1000local.cdata.aatset = 0; // The ACK has been sent
- if(dw1000local.dblbuffon == 0) // If not double buffered
+ //printf("NO LDE done or LDE error\n");
+ if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
{
- if(dw1000local.wait4resp) // wait4response was set with the last TX start command
- {
- // If using wait4response and the ACK has been sent as the response requested it
- // the receiver will be re-enabled, so issue a TRXOFF command to disable and prevent any
- // unexpected interrupts
- dwt_forcetrxoff();
- }
+ dwt_forcetrxoff();
+ }
+ dwt_rxreset(); // Reset the RX
+ dw1000local.wait4resp = 0;
+ dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
+ if(dw1000local.dwt_rxcallback != NULL)
+ {
+ dw1000local.dwt_rxcallback(&dw1000local.cdata);
}
}
+ } // end if CRC is good
+ else
+ //
+ // Check for TX frame sent event and signal to upper layer.
+ //
+ if (status & SYS_STATUS_TXFRS) // Transmit Frame Sent
+ {
+ clear |= SYS_STATUS_ALL_TX; //clear TX event bits
+ dwt_write32bitreg(SYS_STATUS_ID, clear); // Write status register to clear event bits we have seen
+ // NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
+ // New events can trigger and give rise to new interrupts
+ if(dw1000local.cdata.aatset)
+ {
+ dw1000local.cdata.aatset = 0; // The ACK has been sent
+ if(dw1000local.dblbuffon == 0) // If not double buffered
+ {
+ if(dw1000local.wait4resp) // wait4response was set with the last TX start command
+ {
+ // If using wait4response and the ACK has been sent as the response requested it
+ // the receiver will be re-enabled, so issue a TRXOFF command to disable and prevent any
+ // unexpected interrupts
+ dwt_forcetrxoff();
+ }
+ }
+ }
- dw1000local.cdata.event = DWT_SIG_TX_DONE ; // Signal TX completed
+ dw1000local.cdata.event = DWT_SIG_TX_DONE ; // Signal TX completed
- // Call the TX call-back function to process the TX event
- if(dw1000local.dwt_txcallback != NULL)
- {
- dw1000local.dwt_txcallback(&dw1000local.cdata);
- }
+ // Call the TX call-back function to process the TX event
+ if(dw1000local.dwt_txcallback != NULL)
+ {
+ dw1000local.dwt_txcallback(&dw1000local.cdata);
+ }
- }
- else if (status & SYS_STATUS_RXRFTO) // Receiver Frame Wait timeout
- {
- clear |= status & SYS_STATUS_RXRFTO ;
- dwt_write32bitreg(SYS_STATUS_ID,clear) ; // Write status register to clear event bits we have seen
- dw1000local.cdata.event = DWT_SIG_RX_TIMEOUT ;
- if(dw1000local.dwt_rxcallback != NULL)
- {
- dw1000local.dwt_rxcallback(&dw1000local.cdata);
}
- dw1000local.wait4resp = 0;
+ else if (status & SYS_STATUS_RXRFTO) // Receiver Frame Wait timeout
+ {
+ clear |= status & SYS_STATUS_RXRFTO ;
+ dwt_write32bitreg(SYS_STATUS_ID, clear) ; // Write status register to clear event bits we have seen
+ dw1000local.cdata.event = DWT_SIG_RX_TIMEOUT ;
+ if(dw1000local.dwt_rxcallback != NULL)
+ {
+ dw1000local.dwt_rxcallback(&dw1000local.cdata);
+ }
+ dw1000local.wait4resp = 0;
- }
- else if(status & SYS_STATUS_ALL_RX_ERR) // Catches all other error events
- {
- clear |= status & SYS_STATUS_ALL_RX_ERR;
- dwt_write32bitreg(SYS_STATUS_ID,clear) ; // Write status register to clear event bits we have seen
+ }
+ else if(status & SYS_STATUS_ALL_RX_ERR) // Catches all other error events
+ {
+ clear |= status & SYS_STATUS_ALL_RX_ERR;
+ dwt_write32bitreg(SYS_STATUS_ID, clear) ; // Write status register to clear event bits we have seen
- dw1000local.wait4resp = 0;
- // NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
- // New events can trigger and give rise to new interrupts
+ dw1000local.wait4resp = 0;
+ // NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
+ // New events can trigger and give rise to new interrupts
- // Fix for bug 622 - LDE done flag gets latched on a bad frame / reset receiver
- if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
- {
- dwt_forcetrxoff(); // This will clear all events
- }
- dwt_rxreset(); // Reset the RX
- // End of fix for bug 622 - LDE done flag gets latched on a bad frame
+ // Fix for bug 622 - LDE done flag gets latched on a bad frame / reset receiver
+ if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
+ {
+ dwt_forcetrxoff(); // This will clear all events
+ }
+ dwt_rxreset(); // Reset the RX
+ // End of fix for bug 622 - LDE done flag gets latched on a bad frame
- if(status & SYS_STATUS_RXPHE)
- {
- dw1000local.cdata.event = DWT_SIG_RX_PHR_ERROR ;
+ if(status & SYS_STATUS_RXPHE)
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_PHR_ERROR ;
+ }
+ else if(status & SYS_STATUS_RXFCE)
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
+ }
+ else if(status & SYS_STATUS_RXRFSL)
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_SYNCLOSS ;
+ }
+ else if(status & SYS_STATUS_RXSFDTO)
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_SFDTIMEOUT ;
+ }
+ else if(status & SYS_STATUS_RXPTO)
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_PTOTIMEOUT ;
+ }
+ else
+ {
+ dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
+ }
+ if(dw1000local.dwt_rxcallback != NULL)
+ {
+ dw1000local.dwt_rxcallback(&dw1000local.cdata);
+ }
+ status &= SYS_STATUS_ALL_TX;
}
- else if(status & SYS_STATUS_RXFCE)
- {
- dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
- }
- else if(status & SYS_STATUS_RXRFSL)
- {
- dw1000local.cdata.event = DWT_SIG_RX_SYNCLOSS ;
- }
- else if(status & SYS_STATUS_RXSFDTO)
- {
- dw1000local.cdata.event = DWT_SIG_RX_SFDTIMEOUT ;
- }
- else if(status & SYS_STATUS_RXPTO)
- {
- dw1000local.cdata.event = DWT_SIG_RX_PTOTIMEOUT ;
- }
- else
- {
- dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
- }
- if(dw1000local.dwt_rxcallback != NULL)
- {
- dw1000local.dwt_rxcallback(&dw1000local.cdata);
- }
- status &= SYS_STATUS_ALL_TX;
- }
} // end dwt_isr()
/*! ------------------------------------------------------------------------------------------------------------------
@@ -2531,37 +2534,37 @@
if(test & 0x1)
{
// Set up MFIO for LED output
- dwt_readfromdevice(GPIO_CTRL_ID,0x00,2,buf);
+ dwt_readfromdevice(GPIO_CTRL_ID, 0x00, 2, buf);
buf[1] &= ~0x3C; //clear the bits
buf[1] |= 0x14;
- dwt_writetodevice(GPIO_CTRL_ID,0x01,1,&buf[1]);
+ dwt_writetodevice(GPIO_CTRL_ID, 0x01, 1, &buf[1]);
// Enable LP Oscillator to run from counter, turn on debounce clock
- dwt_readfromdevice(PMSC_ID,0x02,1,buf);
+ dwt_readfromdevice(PMSC_ID, 0x02, 1, buf);
buf[0] |= 0x84; //
- dwt_writetodevice(PMSC_ID,0x02,1,buf);
+ dwt_writetodevice(PMSC_ID, 0x02, 1, buf);
// Enable LEDs to blink
buf[0] = 0x10; // Blink period.
buf[1] = 0x01; // Enable blink counter
- dwt_writetodevice(PMSC_ID,PMSC_LEDC_OFFSET,2,buf);
+ dwt_writetodevice(PMSC_ID, PMSC_LEDC_OFFSET, 2, buf);
}
- else if ((test & 0x1)== 0)
+ else if ((test & 0x1) == 0)
{
// Clear the GPIO bits that are used for LED control
- dwt_readfromdevice(GPIO_CTRL_ID,0x00,2,buf);
+ dwt_readfromdevice(GPIO_CTRL_ID, 0x00, 2, buf);
buf[1] &= ~(0x14);
- dwt_writetodevice(GPIO_CTRL_ID,0x00,2,buf);
+ dwt_writetodevice(GPIO_CTRL_ID, 0x00, 2, buf);
}
// Test LEDs
if(test & 0x2)
{
buf[0] = 0x0f; // Fire a LED blink trigger
- dwt_writetodevice(PMSC_ID,0x2a,1,buf);
+ dwt_writetodevice(PMSC_ID, 0x2a, 1, buf);
buf[0] = 0x00; // Clear forced trigger bits
- dwt_writetodevice(PMSC_ID,0x2a,1,buf);
+ dwt_writetodevice(PMSC_ID, 0x2a, 1, buf);
}
} // end _dwt_enableleds()
@@ -2585,53 +2588,53 @@
dwt_readfromdevice(PMSC_ID, PMSC_CTRL0_OFFSET, 2, reg);
switch(clocks)
{
- case ENABLE_ALL_SEQ:
- {
- reg[0] = 0x00 ;
- reg[1] = reg[1] & 0xfe;
- }
- break;
- case FORCE_SYS_XTI:
- {
- // System and RX
- reg[0] = 0x01 | (reg[0] & 0xfc);
- }
- break;
- case FORCE_SYS_PLL:
- {
- // System
- reg[0] = 0x02 | (reg[0] & 0xfc);
- }
- break;
- case READ_ACC_ON:
- {
- reg[0] = 0x48 | (reg[0] & 0xb3);
- reg[1] = 0x80 | reg[1];
- }
- break;
- case READ_ACC_OFF:
- {
- reg[0] = reg[0] & 0xb3;
- reg[1] = 0x7f & reg[1];
+ case ENABLE_ALL_SEQ:
+ {
+ reg[0] = 0x00 ;
+ reg[1] = reg[1] & 0xfe;
+ }
+ break;
+ case FORCE_SYS_XTI:
+ {
+ // System and RX
+ reg[0] = 0x01 | (reg[0] & 0xfc);
+ }
+ break;
+ case FORCE_SYS_PLL:
+ {
+ // System
+ reg[0] = 0x02 | (reg[0] & 0xfc);
+ }
+ break;
+ case READ_ACC_ON:
+ {
+ reg[0] = 0x48 | (reg[0] & 0xb3);
+ reg[1] = 0x80 | reg[1];
+ }
+ break;
+ case READ_ACC_OFF:
+ {
+ reg[0] = reg[0] & 0xb3;
+ reg[1] = 0x7f & reg[1];
- }
- break;
- case FORCE_OTP_ON:
- {
- reg[1] = 0x02 | reg[1];
- }
- break;
- case FORCE_OTP_OFF:
- {
- reg[1] = reg[1] & 0xfd;
- }
- break;
- case FORCE_TX_PLL:
- {
- reg[0] = 0x20| (reg[0] & 0xcf);
- }
- break;
- default:
+ }
+ break;
+ case FORCE_OTP_ON:
+ {
+ reg[1] = 0x02 | reg[1];
+ }
+ break;
+ case FORCE_OTP_OFF:
+ {
+ reg[1] = reg[1] & 0xfd;
+ }
+ break;
+ case FORCE_TX_PLL:
+ {
+ reg[0] = 0x20 | (reg[0] & 0xcf);
+ }
+ break;
+ default:
break;
}
@@ -2703,7 +2706,7 @@
if(mode & DWT_RESPONSE_EXPECTED)
{
temp = (uint8)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
- dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
+ dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
dw1000local.wait4resp = 1;
}
@@ -2713,8 +2716,8 @@
// Both SYS_CTRL_TXSTRT and SYS_CTRL_TXDLYS to correctly enable TX
temp |= (uint8)(SYS_CTRL_TXDLYS | SYS_CTRL_TXSTRT) ;
- dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
- checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID,3) ;
+ dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
+ checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID, 3) ;
//status = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register
if ((checkTxOK & SYS_STATUS_TXERR) == 0) // Transmit Delayed Send set over Half a Period away or Power Up error (there is enough time to send but not to power up individual blocks).
{
@@ -2726,7 +2729,7 @@
// I am taking DSHP set to Indicate that the TXDLYS was set too late for the specified DX_TIME.
// Remedial Action - (a) cancel delayed send
temp = (uint8)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
- dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
+ dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
// Note event Delayed TX Time too Late
// Could fall through to start a normal send (below) just sending late.....
// ... instead return and assume return value of 1 will be used to detect and recover from the issue.
@@ -2741,7 +2744,7 @@
else
{
temp |= (uint8)SYS_CTRL_TXSTRT ;
- dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
+ dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
}
return retval;
@@ -2777,33 +2780,33 @@
*/
void dwt_forcetrxoff(void)
{
- decaIrqStatus_t stat ;
+ decaIrqStatus_t stat ;
uint8 temp ;
- uint32 mask;
+ uint32 mask;
temp = (uint8)SYS_CTRL_TRXOFF ; // This assumes the bit is in the lowest byte
- mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask
+ mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask
- // Need to beware of interrupts occurring in the middle of following read modify write cycle
- // We can disable the radio, but before the status is cleared an interrupt can be set (e.g. the
- // event has just happened before the radio was disabled)
- // thus we need to disable interrupt during this operation
+ // Need to beware of interrupts occurring in the middle of following read modify write cycle
+ // We can disable the radio, but before the status is cleared an interrupt can be set (e.g. the
+ // event has just happened before the radio was disabled)
+ // thus we need to disable interrupt during this operation
stat = decamutexon() ;
- dwt_write32bitreg(SYS_MASK_ID, 0) ; // Clear interrupt mask - so we don't get any unwanted events
+ dwt_write32bitreg(SYS_MASK_ID, 0) ; // Clear interrupt mask - so we don't get any unwanted events
- dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ; // Disable the radio
+ dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ; // Disable the radio
// Forcing Transceiver off - so we do not want to see any new events that may have happened
- dwt_write32bitreg(SYS_STATUS_ID,(SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_GOOD)) ;
+ dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_GOOD)) ;
dwt_syncrxbufptrs();
- dwt_write32bitreg(SYS_MASK_ID, mask) ; // Set interrupt mask to what it was
+ dwt_write32bitreg(SYS_MASK_ID, mask) ; // Set interrupt mask to what it was
- // Enable/restore interrupts again...
- decamutexoff(stat) ;
+ // Enable/restore interrupts again...
+ decamutexoff(stat) ;
dw1000local.wait4resp = 0;
} // end deviceforcetrxoff()
@@ -2827,7 +2830,7 @@
dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &buff);
if((buff & (SYS_STATUS_ICRBP >> 24)) != // IC side Receive Buffer Pointer
- ((buff & (SYS_STATUS_HSRBP>>24)) << 1) ) // Host Side Receive Buffer Pointer
+ ((buff & (SYS_STATUS_HSRBP >> 24)) << 1) ) // Host Side Receive Buffer Pointer
{
uint8 hsrb = 0x01;
dwt_writetodevice(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET , 1, &hsrb) ; // We need to swap RX buffer status reg (write one to toggle internally)
@@ -2892,19 +2895,19 @@
temp |= (uint16)SYS_CTRL_RXDLYE ;
}
- dwt_write16bitoffsetreg(SYS_CTRL_ID,0,temp) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, temp) ;
if (delayed) // Check for errors
{
//uint32 status1 = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register
- dwt_readfromdevice(SYS_STATUS_ID,3,1,&temp1) ;
+ dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &temp1) ;
if (temp1 & (SYS_STATUS_HPDWARN >> 24)) // If delay has not passed do delayed else immediate RX on
{
dwt_forcetrxoff(); // Turn the delayed receive off, and do immediate receive, return warning indication
temp = (uint16)SYS_CTRL_RXENAB; // Clear the delay bit
- dwt_write16bitoffsetreg(SYS_CTRL_ID,0,temp) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, temp) ;
return DWT_ERROR;
}
}
@@ -2930,25 +2933,25 @@
{
uint8 temp ;
- dwt_readfromdevice(SYS_CFG_ID,3,1,&temp) ; // Read register
+ dwt_readfromdevice(SYS_CFG_ID, 3, 1, &temp) ; // Read register
if(time > 0)
{
dwt_write16bitoffsetreg(RX_FWTO_ID, 0x0, time) ;
- temp |= (uint8)(SYS_CFG_RXWTOE>>24);
+ temp |= (uint8)(SYS_CFG_RXWTOE >> 24);
// OR in 32bit value (1 bit set), I know this is in high byte.
dw1000local.sysCFGreg |= SYS_CFG_RXWTOE;
- dwt_writetodevice(SYS_CFG_ID,3,1,&temp) ;
+ dwt_writetodevice(SYS_CFG_ID, 3, 1, &temp) ;
}
else
{
- temp &= ~((uint8)(SYS_CFG_RXWTOE>>24));
+ temp &= ~((uint8)(SYS_CFG_RXWTOE >> 24));
// AND in inverted 32bit value (1 bit clear), I know this is in high byte.
dw1000local.sysCFGreg &= ~(SYS_CFG_RXWTOE);
- dwt_writetodevice(SYS_CFG_ID,3,1,&temp) ;
+ dwt_writetodevice(SYS_CFG_ID, 3, 1, &temp) ;
//dwt_write16bitoffsetreg(RX_FWTO_ID,0,0) ; // Clearing the time is not needed
}
@@ -3015,7 +3018,7 @@
{
mask &= ~bitmask ; // Clear the bit
}
- dwt_write32bitreg(SYS_MASK_ID,mask) ; // New value
+ dwt_write32bitreg(SYS_MASK_ID, mask) ; // New value
decamutexoff(stat) ;
}
@@ -3061,7 +3064,7 @@
{
uint32 temp;
- temp= dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_PHE_OFFSET); // Read sync loss (31-16), PHE (15-0)
+ temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_PHE_OFFSET); // Read sync loss (31-16), PHE (15-0)
counters->PHE = temp & 0xFFF;
counters->RSL = (temp >> 16) & 0xFFF;
@@ -3100,12 +3103,12 @@
*/
void dwt_rxreset(void)
{
- uint8 resetrx = 0xe0;
- // Set RX reset
- dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
+ uint8 resetrx = 0xe0;
+ // Set RX reset
+ dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
- resetrx = 0xf0; // Clear RX reset
- dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
+ resetrx = 0xf0; // Clear RX reset
+ dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -3166,13 +3169,13 @@
{
uint8 write_buf;
- dwt_readfromdevice(FS_CTRL_ID,FS_XTALT_OFFSET,1,&write_buf);
+ dwt_readfromdevice(FS_CTRL_ID, FS_XTALT_OFFSET, 1, &write_buf);
write_buf &= ~FS_XTALT_MASK ;
write_buf |= (FS_XTALT_MASK & value) ; // We should not change high bits, cause it will cause malfunction
- dwt_writetodevice(FS_CTRL_ID,FS_XTALT_OFFSET,1,&write_buf);
+ dwt_writetodevice(FS_CTRL_ID, FS_XTALT_OFFSET, 1, &write_buf);
}
@@ -3194,8 +3197,8 @@
#ifdef DWT_API_ERROR_CHECK
if ((chan < 1) || (chan > 7) || (6 == chan))
{
- return DWT_ERROR ; // validate channel number parameter
- }
+ return DWT_ERROR ; // validate channel number parameter
+ }
#endif
//
@@ -3222,15 +3225,15 @@
// Configure TX clocks
//
write_buf[0] = 0x22;
- dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,write_buf);
+ dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, write_buf);
write_buf[0] = 0x07;
- dwt_writetodevice(PMSC_ID,0x1,1,write_buf);
+ dwt_writetodevice(PMSC_ID, 0x1, 1, write_buf);
// Disable fine grain TX seq
dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_DIS_MASK);
- write_buf[0] = TC_PGTEST_CW;
+ write_buf[0] = TC_PGTEST_CW;
// Configure CW mode
dwt_writetodevice(TX_CAL_ID, TC_PGTEST_OFFSET, TC_PGTEST_LEN, write_buf);
@@ -3283,7 +3286,7 @@
// Configure continuous frame TX
//
write_buf[0] = (uint8)(DIAG_TMC_TX_PSTM) ;
- dwt_writetodevice(DIG_DIAG_ID, DIAG_TMC_OFFSET, 1,write_buf); // Turn the tx power spectrum test mode - continuous sending of frames
+ dwt_writetodevice(DIG_DIAG_ID, DIAG_TMC_OFFSET, 1, write_buf); // Turn the tx power spectrum test mode - continuous sending of frames
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -3315,31 +3318,31 @@
// These writes should be single writes and in sequence
wr_buf[0] = 0x80; // Enable TLD Bias
- dwt_writetodevice(RF_CONF_ID,0x11,1,wr_buf);
+ dwt_writetodevice(RF_CONF_ID, 0x11, 1, wr_buf);
wr_buf[0] = 0x0A; // Enable TLD Bias and ADC Bias
- dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf);
+ dwt_writetodevice(RF_CONF_ID, 0x12, 1, wr_buf);
wr_buf[0] = 0x0f; // Enable Outputs (only after Biases are up and running)
- dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf); //
+ dwt_writetodevice(RF_CONF_ID, 0x12, 1, wr_buf); //
// Reading All SAR inputs
wr_buf[0] = 0x00;
- dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
+ dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C, 1, wr_buf);
wr_buf[0] = 0x01; // Set SAR enable
- dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
+ dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C, 1, wr_buf);
if(fastSPI == 1)
{
deca_sleep(1); // If using PLL clocks(and fast SPI rate) then this sleep is needed
// Read voltage and temperature.
- dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
+ dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET, 2, wr_buf);
}
else //change to a slow clock
{
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read are reliable
// Read voltage and temperature.
- dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
+ dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET, 2, wr_buf);
// Default clocks (ENABLE_ALL_SEQ)
_dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
}
@@ -3348,9 +3351,9 @@
temp_raw = wr_buf[1];
wr_buf[0] = 0x00; // Clear SAR enable
- dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
+ dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C, 1, wr_buf);
- return ((temp_raw<<8)|(vbat_raw));
+ return ((temp_raw << 8) | (vbat_raw));
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -3369,7 +3372,7 @@
uint8 dwt_readwakeuptemp(void)
{
uint8 temp_raw;
- dwt_readfromdevice(TX_CAL_ID,TC_SARL_SAR_LTEMP_OFFSET,1,&temp_raw);
+ dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LTEMP_OFFSET, 1, &temp_raw);
return (temp_raw);
}
@@ -3389,7 +3392,7 @@
uint8 dwt_readwakeupvbat(void)
{
uint8 vbat_raw;
- dwt_readfromdevice(TX_CAL_ID,TC_SARL_SAR_LVBAT_OFFSET,1,&vbat_raw);
+ dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET, 1, &vbat_raw);
return (vbat_raw);
}
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device_api.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device_api.h"
index f04c639..032fbbd 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device_api.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device_api.h"
@@ -167,26 +167,28 @@
#define DWT_OPSET_TIGHT 0x1
#define DWT_OPSET_DEFLT 0x2
-typedef struct{
+typedef struct
+{
- uint32 status; //initial value of register as ISR is entered
- uint8 event; //event type
- uint8 aatset; //auto ACK TX bit is set
- uint16 datalength; //length of frame
- uint8 fctrl[2]; //frame control bytes
- uint8 dblbuff ; //set if double buffer is enabled
+ uint32 status; //initial value of register as ISR is entered
+ uint8 event; //event type
+ uint8 aatset; //auto ACK TX bit is set
+ uint16 datalength; //length of frame
+ uint8 fctrl[2]; //frame control bytes
+ uint8 dblbuff ; //set if double buffer is enabled
-}dwt_callback_data_t;
+} dwt_callback_data_t;
-typedef enum {
- CHAN_CTRL_TXCHAN_1 = 0x01, /* Selects the transmit channel 1 */
- CHAN_CTRL_TXCHAN_2 = 0x02, /* Selects the transmit channel 2 */
- CHAN_CTRL_TXCHAN_3 = 0x03, /* Selects the transmit channel 3 */
- CHAN_CTRL_TXCHAN_4 = 0x04, /* Selects the transmit channel 4 */
- CHAN_CTRL_TXCHAN_5 = 0x05, /* Selects the transmit channel 5 */
- CHAN_CTRL_TXCHAN_7 = 0x07 /* Selects the transmit channel 7 */
-}eCHAN;
+typedef enum
+{
+ CHAN_CTRL_TXCHAN_1 = 0x01, /* Selects the transmit channel 1 */
+ CHAN_CTRL_TXCHAN_2 = 0x02, /* Selects the transmit channel 2 */
+ CHAN_CTRL_TXCHAN_3 = 0x03, /* Selects the transmit channel 3 */
+ CHAN_CTRL_TXCHAN_4 = 0x04, /* Selects the transmit channel 4 */
+ CHAN_CTRL_TXCHAN_5 = 0x05, /* Selects the transmit channel 5 */
+ CHAN_CTRL_TXCHAN_7 = 0x07 /* Selects the transmit channel 7 */
+} eCHAN;
/*! ------------------------------------------------------------------------------------------------------------------
@@ -209,19 +211,19 @@
uint8 dataRate ; //!< Data Rate {DWT_BR_110K, DWT_BR_850K or DWT_BR_6M8}
uint8 phrMode ; //!< PHR mode {0x0 - standard DWT_PHRMODE_STD, 0x3 - extended frames DWT_PHRMODE_EXT}
uint16 sfdTO ; //!< SFD timeout value (in symbols)
-}__attribute__ ((packed)) dwt_config_t ;
+} __attribute__ ((packed)) dwt_config_t ;
#pragma pack()
typedef struct
{
- uint8 PGdly;
- //TX POWER
- //31:24 BOOST_0.125ms_PWR
- //23:16 BOOST_0.25ms_PWR-TX_SHR_PWR
- //15:8 BOOST_0.5ms_PWR-TX_PHR_PWR
- //7:0 DEFAULT_PWR-TX_DATA_PWR
- uint32 power;
+ uint8 PGdly;
+ //TX POWER
+ //31:24 BOOST_0.125ms_PWR
+ //23:16 BOOST_0.25ms_PWR-TX_SHR_PWR
+ //15:8 BOOST_0.5ms_PWR-TX_PHR_PWR
+ //7:0 DEFAULT_PWR-TX_DATA_PWR
+ uint32 power;
}
dwt_txconfig_t ;
@@ -229,33 +231,33 @@
typedef struct
{
- uint16 maxNoise ; // LDE max value of noise
- uint16 firstPathAmp1 ; // Amplitude at floor(index FP) + 1
- uint16 stdNoise ; // Standard deviation of noise
- uint16 firstPathAmp2 ; // Amplitude at floor(index FP) + 2
- uint16 firstPathAmp3 ; // Amplitude at floor(index FP) + 3
- uint16 maxGrowthCIR ; // Channel Impulse Response max growth CIR
+ uint16 maxNoise ; // LDE max value of noise
+ uint16 firstPathAmp1 ; // Amplitude at floor(index FP) + 1
+ uint16 stdNoise ; // Standard deviation of noise
+ uint16 firstPathAmp2 ; // Amplitude at floor(index FP) + 2
+ uint16 firstPathAmp3 ; // Amplitude at floor(index FP) + 3
+ uint16 maxGrowthCIR ; // Channel Impulse Response max growth CIR
uint16 rxPreamCount ; // Count of preamble symbols accumulated
//uint32 debug1;
//uint32 debug2;
uint16 firstPath ; // First path index (10.6 bits fixed point integer)
-}dwt_rxdiag_t ;
+} dwt_rxdiag_t ;
typedef struct
{
- //all of the below are mapped to a 12-bit register in DW1000
+ //all of the below are mapped to a 12-bit register in DW1000
uint16 PHE ; //number of received header errors
- uint16 RSL ; //number of received frame sync loss events
+ uint16 RSL ; //number of received frame sync loss events
uint16 CRCG ; //number of good CRC received frames
uint16 CRCB ; //number of bad CRC (CRC error) received frames
- uint16 ARFE ; //number of address filter errors
- uint16 OVER ; //number of receiver overflows (used in double buffer mode)
+ uint16 ARFE ; //number of address filter errors
+ uint16 OVER ; //number of receiver overflows (used in double buffer mode)
uint16 SFDTO ; //SFD timeouts
uint16 PTO ; //Preamble timeouts
uint16 RTO ; //RX frame wait timeouts
uint16 TXF ; //number of transmitted frames
- uint16 HPW ; //half period warn
+ uint16 HPW ; //half period warn
uint16 TXW ; //power up warn
} dwt_deviceentcnts_t ;
@@ -541,7 +543,7 @@
*
* no return value
*/
-void dwt_readtxtimestamp(uint8 * timestamp);
+void dwt_readtxtimestamp(uint8 *timestamp);
/*! ------------------------------------------------------------------------------------------------------------------
* @fn dwt_readtxtimestamphi32()
@@ -581,7 +583,7 @@
*
* no return value
*/
-void dwt_readrxtimestamp(uint8 * timestamp);
+void dwt_readrxtimestamp(uint8 *timestamp);
/*! ------------------------------------------------------------------------------------------------------------------
* @fn dwt_readrxtimestamphi32()
@@ -635,7 +637,7 @@
*
* no return value
*/
-void dwt_readsystime(uint8 * timestamp);
+void dwt_readsystime(uint8 *timestamp);
/*! ------------------------------------------------------------------------------------------------------------------
* @fn dwt_checkoverrun()
@@ -802,41 +804,41 @@
*
* no return value
*/
- void dwt_configuresleepcnt(uint16 sleepcnt);
+void dwt_configuresleepcnt(uint16 sleepcnt);
- /*! ------------------------------------------------------------------------------------------------------------------
- * @fn dwt_configuresleep()
- *
- * @brief configures the device for both DEEP_SLEEP and SLEEP modes, and on-wake mode
- * i.e. before entering the sleep, the device should be programmed for TX or RX, then upon "waking up" the TX/RX settings
- * will be preserved and the device can immediately perform the desired action TX/RX
- *
- * NOTE: e.g. Tag operation - after deep sleep, the device needs to just load the TX buffer and send the frame
- *
- *
- * mode: the array and LDE code (OTP/ROM) and LDO tune, and set sleep persist
- * DWT_PRESRV_SLEEP 0x0100 - preserve sleep
- * DWT_LOADOPSET 0x0080 - load operating parameter set on wakeup
- * DWT_CONFIG 0x0040 - download the AON array into the HIF (configuration download)
- * DWT_LOADEUI 0x0008
- * DWT_GOTORX 0x0002
- * DWT_TANDV 0x0001
- *
- * wake: wake up parameters
- * DWT_XTAL_EN 0x10 - keep XTAL running during sleep
- * DWT_WAKE_SLPCNT 0x8 - wake up after sleep count
- * DWT_WAKE_CS 0x4 - wake up on chip select
- * DWT_WAKE_WK 0x2 - wake up on WAKEUP PIN
- * DWT_SLP_EN 0x1 - enable sleep/deep sleep functionality
- *
- * input parameters
- * @param mode - config on-wake parameters
- * @param wake - config wake up parameters
- *
- * output parameters
- *
- * no return value
- */
+/*! ------------------------------------------------------------------------------------------------------------------
+ * @fn dwt_configuresleep()
+ *
+ * @brief configures the device for both DEEP_SLEEP and SLEEP modes, and on-wake mode
+ * i.e. before entering the sleep, the device should be programmed for TX or RX, then upon "waking up" the TX/RX settings
+ * will be preserved and the device can immediately perform the desired action TX/RX
+ *
+ * NOTE: e.g. Tag operation - after deep sleep, the device needs to just load the TX buffer and send the frame
+ *
+ *
+ * mode: the array and LDE code (OTP/ROM) and LDO tune, and set sleep persist
+ * DWT_PRESRV_SLEEP 0x0100 - preserve sleep
+ * DWT_LOADOPSET 0x0080 - load operating parameter set on wakeup
+ * DWT_CONFIG 0x0040 - download the AON array into the HIF (configuration download)
+ * DWT_LOADEUI 0x0008
+ * DWT_GOTORX 0x0002
+ * DWT_TANDV 0x0001
+ *
+ * wake: wake up parameters
+ * DWT_XTAL_EN 0x10 - keep XTAL running during sleep
+ * DWT_WAKE_SLPCNT 0x8 - wake up after sleep count
+ * DWT_WAKE_CS 0x4 - wake up on chip select
+ * DWT_WAKE_WK 0x2 - wake up on WAKEUP PIN
+ * DWT_SLP_EN 0x1 - enable sleep/deep sleep functionality
+ *
+ * input parameters
+ * @param mode - config on-wake parameters
+ * @param wake - config wake up parameters
+ *
+ * output parameters
+ *
+ * no return value
+ */
void dwt_configuresleep(uint16 mode, uint8 wake);
/*! ------------------------------------------------------------------------------------------------------------------
@@ -1162,7 +1164,7 @@
*
* no return value
*/
-void dwt_readdiagnostics(dwt_rxdiag_t * diagnostics);
+void dwt_readdiagnostics(dwt_rxdiag_t *diagnostics);
/*! ------------------------------------------------------------------------------------------------------------------
* @fn dwt_loadopsettabfromotp()
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_param_types.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_param_types.h"
index 0f98830..d923f67 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_param_types.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_param_types.h"
@@ -27,15 +27,16 @@
#define PCODES 25 //supported preamble codes
-typedef struct {
- uint32 lo32;
- uint16 target[NUM_PRF];
+typedef struct
+{
+ uint32 lo32;
+ uint16 target[NUM_PRF];
} agc_cfg_struct ;
extern const agc_cfg_struct agc_config ;
//SFD threshold settings for 110k, 850k, 6.8Mb standard and non-standard
-extern const uint16 sftsh[NUM_BR][NUM_SFD];
+extern const uint16 sftsh[NUM_BR][NUM_SFD];
extern const uint16 dtune1[NUM_PRF];
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c"
index e63772d..0e6603d 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c"
@@ -27,12 +27,12 @@
//-----------------------------------------
const uint32 tx_config[NUM_CH] =
{
- RF_TXCTRL_CH1, /* Tx value match UM */
- RF_TXCTRL_CH2,
- RF_TXCTRL_CH3,
- RF_TXCTRL_CH4,
- RF_TXCTRL_CH5,
- RF_TXCTRL_CH7,
+ RF_TXCTRL_CH1, /* Tx value match UM */
+ RF_TXCTRL_CH2,
+ RF_TXCTRL_CH3,
+ RF_TXCTRL_CH4,
+ RF_TXCTRL_CH5,
+ RF_TXCTRL_CH7,
};
//RF -> Channel_Specific_Cfg -> Channel_Cfg -> RF_PLL -> RF PLL2
@@ -97,32 +97,33 @@
};
const uint32 digital_bb_config[NUM_PRF][NUM_PACS] =
+{
+ //16 PRF
{
- //16 PRF
- {
- //PAC 8
- 0x311A002D,
- //PAC 16
- 0x331A0052,
- //PAC 32
- 0x351A009A,
- //PAC 64
- 0x371A011D
- },
- //64 PRF
- {
- //PAC 8
- 0x313B006B,
- //PAC 16
- 0x333B00BE,
- //PAC 32
- 0x353B015E,
- //PAC 64
- 0x373B0296
- }
+ //PAC 8
+ 0x311A002D,
+ //PAC 16
+ 0x331A0052,
+ //PAC 32
+ 0x351A009A,
+ //PAC 64
+ 0x371A011D
+ },
+ //64 PRF
+ {
+ //PAC 8
+ 0x313B006B,
+ //PAC 16
+ 0x333B00BE,
+ //PAC 32
+ 0x353B015E,
+ //PAC 64
+ 0x373B0296
+ }
};
-const uint16 lde_replicaCoeff[PCODES] = {
+const uint16 lde_replicaCoeff[PCODES] =
+{
// 0
(int)(0.0 * 65536),
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_range_tables.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_range_tables.c"
index 3a61c3d..e230d1d 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_range_tables.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_range_tables.c"
@@ -43,166 +43,166 @@
{
// Ch 1 - range25cm16PRFnb
{
- 1,
- 3,
- 4,
- 5,
- 7,
- 9,
- 11,
- 12,
- 13,
- 15,
- 18,
- 20,
- 23,
- 25,
- 28,
- 30,
- 33,
- 36,
- 40,
- 43,
- 47,
- 50,
- 54,
- 58,
- 63,
- 66,
- 71,
- 76,
- 82,
- 89,
- 98,
- 109,
- 127,
- 155,
- 222,
- 255,
- 255
+ 1,
+ 3,
+ 4,
+ 5,
+ 7,
+ 9,
+ 11,
+ 12,
+ 13,
+ 15,
+ 18,
+ 20,
+ 23,
+ 25,
+ 28,
+ 30,
+ 33,
+ 36,
+ 40,
+ 43,
+ 47,
+ 50,
+ 54,
+ 58,
+ 63,
+ 66,
+ 71,
+ 76,
+ 82,
+ 89,
+ 98,
+ 109,
+ 127,
+ 155,
+ 222,
+ 255,
+ 255
},
// Ch 2 - range25cm16PRFnb
{
- 1,
- 2,
- 4,
- 5,
- 6,
- 8,
- 9,
- 10,
- 12,
- 13,
- 15,
- 18,
- 20,
- 22,
- 24,
- 27,
- 29,
- 32,
- 35,
- 38,
- 41,
- 44,
- 47,
- 51,
- 55,
- 58,
- 62,
- 66,
- 71,
- 78,
- 85,
- 96,
- 111,
- 135,
- 194,
- 240,
- 255
+ 1,
+ 2,
+ 4,
+ 5,
+ 6,
+ 8,
+ 9,
+ 10,
+ 12,
+ 13,
+ 15,
+ 18,
+ 20,
+ 22,
+ 24,
+ 27,
+ 29,
+ 32,
+ 35,
+ 38,
+ 41,
+ 44,
+ 47,
+ 51,
+ 55,
+ 58,
+ 62,
+ 66,
+ 71,
+ 78,
+ 85,
+ 96,
+ 111,
+ 135,
+ 194,
+ 240,
+ 255
},
// Ch 3 - range25cm16PRFnb
{
- 1,
- 2,
- 3,
- 4,
- 5,
- 7,
- 8,
- 9,
- 10,
- 12,
- 14,
- 16,
- 18,
- 20,
- 22,
- 24,
- 26,
- 28,
- 31,
- 33,
- 36,
- 39,
- 42,
- 45,
- 49,
- 52,
- 55,
- 59,
- 63,
- 69,
- 76,
- 85,
- 98,
- 120,
- 173,
- 213,
- 255
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 7,
+ 8,
+ 9,
+ 10,
+ 12,
+ 14,
+ 16,
+ 18,
+ 20,
+ 22,
+ 24,
+ 26,
+ 28,
+ 31,
+ 33,
+ 36,
+ 39,
+ 42,
+ 45,
+ 49,
+ 52,
+ 55,
+ 59,
+ 63,
+ 69,
+ 76,
+ 85,
+ 98,
+ 120,
+ 173,
+ 213,
+ 255
},
// Ch 5 - range25cm16PRFnb
{
- 1,
- 1,
- 2,
- 3,
- 4,
- 5,
- 6,
- 6,
- 7,
- 8,
- 9,
- 11,
- 12,
- 14,
- 15,
- 16,
- 18,
- 20,
- 21,
- 23,
- 25,
- 27,
- 29,
- 31,
- 34,
- 36,
- 38,
- 41,
- 44,
- 48,
- 53,
- 59,
- 68,
- 83,
- 120,
- 148,
- 255
+ 1,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 6,
+ 7,
+ 8,
+ 9,
+ 11,
+ 12,
+ 14,
+ 15,
+ 16,
+ 18,
+ 20,
+ 21,
+ 23,
+ 25,
+ 27,
+ 29,
+ 31,
+ 34,
+ 36,
+ 38,
+ 41,
+ 44,
+ 48,
+ 53,
+ 59,
+ 68,
+ 83,
+ 120,
+ 148,
+ 255
}
}; // end range25cm16PRFnb
@@ -215,146 +215,146 @@
{
// Ch 4 - range25cm16PRFwb
{
- 7,
- 7,
- 8,
- 9,
- 9,
- 10,
- 11,
- 11,
- 12,
- 13,
- 14,
- 15,
- 16,
- 17,
- 18,
- 19,
- 20,
- 21,
- 22,
- 23,
- 24,
- 26,
- 27,
- 28,
- 30,
- 31,
- 32,
- 34,
- 36,
- 38,
- 40,
- 42,
- 44,
- 46,
- 48,
- 50,
- 52,
- 55,
- 57,
- 59,
- 61,
- 63,
- 66,
- 68,
- 71,
- 74,
- 78,
- 81,
- 85,
- 89,
- 94,
- 99,
- 104,
- 110,
- 116,
- 123,
- 130,
- 139,
- 150,
- 164,
- 182,
- 207,
- 238,
- 255,
- 255,
- 255,
- 255,
- 255
+ 7,
+ 7,
+ 8,
+ 9,
+ 9,
+ 10,
+ 11,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 26,
+ 27,
+ 28,
+ 30,
+ 31,
+ 32,
+ 34,
+ 36,
+ 38,
+ 40,
+ 42,
+ 44,
+ 46,
+ 48,
+ 50,
+ 52,
+ 55,
+ 57,
+ 59,
+ 61,
+ 63,
+ 66,
+ 68,
+ 71,
+ 74,
+ 78,
+ 81,
+ 85,
+ 89,
+ 94,
+ 99,
+ 104,
+ 110,
+ 116,
+ 123,
+ 130,
+ 139,
+ 150,
+ 164,
+ 182,
+ 207,
+ 238,
+ 255,
+ 255,
+ 255,
+ 255,
+ 255
},
// Ch 7 - range25cm16PRFwb
{
- 4,
- 5,
- 5,
- 5,
- 6,
- 6,
- 7,
- 7,
- 7,
- 8,
- 9,
- 9,
- 10,
- 10,
- 11,
- 11,
- 12,
- 13,
- 13,
- 14,
- 15,
- 16,
- 17,
- 17,
- 18,
- 19,
- 20,
- 21,
- 22,
- 23,
- 25,
- 26,
- 27,
- 29,
- 30,
- 31,
- 32,
- 34,
- 35,
- 36,
- 38,
- 39,
- 40,
- 42,
- 44,
- 46,
- 48,
- 50,
- 52,
- 55,
- 58,
- 61,
- 64,
- 68,
- 72,
- 75,
- 80,
- 85,
- 92,
- 101,
- 112,
- 127,
- 147,
- 168,
- 182,
- 194,
- 205,
- 255
+ 4,
+ 5,
+ 5,
+ 5,
+ 6,
+ 6,
+ 7,
+ 7,
+ 7,
+ 8,
+ 9,
+ 9,
+ 10,
+ 10,
+ 11,
+ 11,
+ 12,
+ 13,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 25,
+ 26,
+ 27,
+ 29,
+ 30,
+ 31,
+ 32,
+ 34,
+ 35,
+ 36,
+ 38,
+ 39,
+ 40,
+ 42,
+ 44,
+ 46,
+ 48,
+ 50,
+ 52,
+ 55,
+ 58,
+ 61,
+ 64,
+ 68,
+ 72,
+ 75,
+ 80,
+ 85,
+ 92,
+ 101,
+ 112,
+ 127,
+ 147,
+ 168,
+ 182,
+ 194,
+ 205,
+ 255
}
}; // end range25cm16PRFwb
@@ -366,122 +366,122 @@
{
// Ch 1 - range25cm64PRFnb
{
- 1,
- 2,
- 2,
- 3,
- 4,
- 5,
- 7,
- 10,
- 13,
- 16,
- 19,
- 22,
- 24,
- 27,
- 30,
- 32,
- 35,
- 38,
- 43,
- 48,
- 56,
- 78,
- 101,
- 120,
- 157,
- 255
+ 1,
+ 2,
+ 2,
+ 3,
+ 4,
+ 5,
+ 7,
+ 10,
+ 13,
+ 16,
+ 19,
+ 22,
+ 24,
+ 27,
+ 30,
+ 32,
+ 35,
+ 38,
+ 43,
+ 48,
+ 56,
+ 78,
+ 101,
+ 120,
+ 157,
+ 255
},
// Ch 2 - range25cm64PRFnb
{
- 1,
- 2,
- 2,
- 3,
- 4,
- 4,
- 6,
- 9,
- 12,
- 14,
- 17,
- 19,
- 21,
- 24,
- 26,
- 28,
- 31,
- 33,
- 37,
- 42,
- 49,
- 68,
- 89,
- 105,
- 138,
- 255
+ 1,
+ 2,
+ 2,
+ 3,
+ 4,
+ 4,
+ 6,
+ 9,
+ 12,
+ 14,
+ 17,
+ 19,
+ 21,
+ 24,
+ 26,
+ 28,
+ 31,
+ 33,
+ 37,
+ 42,
+ 49,
+ 68,
+ 89,
+ 105,
+ 138,
+ 255
},
// Ch 3 - range25cm64PRFnb
{
- 1,
- 1,
- 2,
- 3,
- 3,
- 4,
- 5,
- 8,
- 10,
- 13,
- 15,
- 17,
- 19,
- 21,
- 23,
- 25,
- 27,
- 30,
- 33,
- 37,
- 44,
- 60,
- 79,
- 93,
- 122,
- 255
+ 1,
+ 1,
+ 2,
+ 3,
+ 3,
+ 4,
+ 5,
+ 8,
+ 10,
+ 13,
+ 15,
+ 17,
+ 19,
+ 21,
+ 23,
+ 25,
+ 27,
+ 30,
+ 33,
+ 37,
+ 44,
+ 60,
+ 79,
+ 93,
+ 122,
+ 255
},
// Ch 5 - range25cm64PRFnb
{
- 1,
- 1,
- 1,
- 2,
- 2,
- 3,
- 4,
- 6,
- 7,
- 9,
- 10,
- 12,
- 13,
- 15,
- 16,
- 17,
- 19,
- 21,
- 23,
- 26,
- 30,
- 42,
- 55,
- 65,
- 85,
- 255
+ 1,
+ 1,
+ 1,
+ 2,
+ 2,
+ 3,
+ 4,
+ 6,
+ 7,
+ 9,
+ 10,
+ 12,
+ 13,
+ 15,
+ 16,
+ 17,
+ 19,
+ 21,
+ 23,
+ 26,
+ 30,
+ 42,
+ 55,
+ 65,
+ 85,
+ 255
}
}; // end range25cm64PRFnb
@@ -493,128 +493,128 @@
{
// Ch 4 - range25cm64PRFwb
{
- 7,
- 8,
- 8,
- 9,
- 9,
- 10,
- 11,
- 12,
- 13,
- 13,
- 14,
- 15,
- 16,
- 16,
- 17,
- 18,
- 19,
- 19,
- 20,
- 21,
- 22,
- 24,
- 25,
- 27,
- 28,
- 29,
- 30,
- 32,
- 33,
- 34,
- 35,
- 37,
- 39,
- 41,
- 43,
- 45,
- 48,
- 50,
- 53,
- 56,
- 60,
- 64,
- 68,
- 74,
- 81,
- 89,
- 98,
- 109,
- 122,
- 136,
- 146,
- 154,
- 162,
- 178,
- 220,
- 249,
- 255,
- 255,
- 255
+ 7,
+ 8,
+ 8,
+ 9,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 13,
+ 14,
+ 15,
+ 16,
+ 16,
+ 17,
+ 18,
+ 19,
+ 19,
+ 20,
+ 21,
+ 22,
+ 24,
+ 25,
+ 27,
+ 28,
+ 29,
+ 30,
+ 32,
+ 33,
+ 34,
+ 35,
+ 37,
+ 39,
+ 41,
+ 43,
+ 45,
+ 48,
+ 50,
+ 53,
+ 56,
+ 60,
+ 64,
+ 68,
+ 74,
+ 81,
+ 89,
+ 98,
+ 109,
+ 122,
+ 136,
+ 146,
+ 154,
+ 162,
+ 178,
+ 220,
+ 249,
+ 255,
+ 255,
+ 255
},
// Ch 7 - range25cm64PRFwb
{
- 4,
- 5,
- 5,
- 5,
- 6,
- 6,
- 7,
- 7,
- 8,
- 8,
- 9,
- 9,
- 10,
- 10,
- 10,
- 11,
- 11,
- 12,
- 13,
- 13,
- 14,
- 15,
- 16,
- 16,
- 17,
- 18,
- 19,
- 19,
- 20,
- 21,
- 22,
- 23,
- 24,
- 25,
- 26,
- 28,
- 29,
- 31,
- 33,
- 35,
- 37,
- 39,
- 42,
- 46,
- 50,
- 54,
- 60,
- 67,
- 75,
- 83,
- 90,
- 95,
- 100,
- 110,
- 135,
- 153,
- 172,
- 192,
- 255
+ 4,
+ 5,
+ 5,
+ 5,
+ 6,
+ 6,
+ 7,
+ 7,
+ 8,
+ 8,
+ 9,
+ 9,
+ 10,
+ 10,
+ 10,
+ 11,
+ 11,
+ 12,
+ 13,
+ 13,
+ 14,
+ 15,
+ 16,
+ 16,
+ 17,
+ 18,
+ 19,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 28,
+ 29,
+ 31,
+ 33,
+ 35,
+ 37,
+ 39,
+ 42,
+ 46,
+ 50,
+ 54,
+ 60,
+ 67,
+ 75,
+ 83,
+ 90,
+ 95,
+ 100,
+ 110,
+ 135,
+ 153,
+ 172,
+ 192,
+ 255
}
}; // end range25cm64PRFwb
@@ -624,8 +624,8 @@
*
* @brief This function is used to return the range bias correction need for TWR with DW1000 units.
*
- * input parameters:
- * @param chan - specifies the operating channel (e.g. 1, 2, 3, 4, 5, 6 or 7)
+ * input parameters:
+ * @param chan - specifies the operating channel (e.g. 1, 2, 3, 4, 5, 6 or 7)
* @param range - the calculated distance before correction
* @param prf - this is the PRF e.g. DWT_PRF_16M or DWT_PRF_64M
*
@@ -652,40 +652,40 @@
{
switch(chan)
{
- case 4:
- case 7:
- {
- chanIdx = chan_idxwb[chan];
- while (rangeint25cm > range25cm16PRFwb[chanIdx][i]) i++ ; // Find index in table corresponding to range
- cmoffseti = i + CM_OFFSET_16M_WB ; // Nearest centimetre correction
- }
- break;
- default:
- {
- chanIdx = chan_idxnb[chan];
- while (rangeint25cm > range25cm16PRFnb[chanIdx][i]) i++ ; // Find index in table corresponding to range
- cmoffseti = i + CM_OFFSET_16M_NB ; // Nearest centimetre correction
- }
+ case 4:
+ case 7:
+ {
+ chanIdx = chan_idxwb[chan];
+ while (rangeint25cm > range25cm16PRFwb[chanIdx][i]) i++ ; // Find index in table corresponding to range
+ cmoffseti = i + CM_OFFSET_16M_WB ; // Nearest centimetre correction
+ }
+ break;
+ default:
+ {
+ chanIdx = chan_idxnb[chan];
+ while (rangeint25cm > range25cm16PRFnb[chanIdx][i]) i++ ; // Find index in table corresponding to range
+ cmoffseti = i + CM_OFFSET_16M_NB ; // Nearest centimetre correction
+ }
}//end of switch
}
else // 64M PRF
{
switch(chan)
{
- case 4:
- case 7:
- {
- chanIdx = chan_idxwb[chan];
- while (rangeint25cm > range25cm64PRFwb[chanIdx][i]) i++ ; // Find index in table corresponding to range
- cmoffseti = i + CM_OFFSET_64M_WB ; // Nearest centimetre correction
- }
- break;
- default:
- {
- chanIdx = chan_idxnb[chan];
- while (rangeint25cm > range25cm64PRFnb[chanIdx][i]) i++ ; // Find index in table corresponding to range
- cmoffseti = i + CM_OFFSET_64M_NB ; // Nearest centimetre correction
- }
+ case 4:
+ case 7:
+ {
+ chanIdx = chan_idxwb[chan];
+ while (rangeint25cm > range25cm64PRFwb[chanIdx][i]) i++ ; // Find index in table corresponding to range
+ cmoffseti = i + CM_OFFSET_64M_WB ; // Nearest centimetre correction
+ }
+ break;
+ default:
+ {
+ chanIdx = chan_idxnb[chan];
+ while (rangeint25cm > range25cm64PRFnb[chanIdx][i]) i++ ; // Find index in table corresponding to range
+ cmoffseti = i + CM_OFFSET_64M_NB ; // Nearest centimetre correction
+ }
}//end of switch
} // end else
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_regs.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_regs.h"
index 4572285..9fda932 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_regs.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_regs.h"
@@ -381,7 +381,7 @@
/****************************************************************************//**
* @brief Bit definitions for register RX_TTCKI
* The value here is the interval over which the timing offset reported
- * in the RXTOFS field of Register file: 0x14 � RX_TTCKO is measured.
+ * in the RXTOFS field of Register file: 0x14 ?RX_TTCKO is measured.
* The clock offset is calculated by dividing RXTTCKI by RXTOFS.
* The value in RXTTCKI will take just one of two values depending on the PRF: 0x01F00000 @ 16 MHz PRF,
* and 0x01FC0000 @ 64 MHz PRF.
@@ -767,10 +767,10 @@
#define GIMOD8 GIRQx8 /* Value 0 = Level, 1 = Edge. */
/* offset from EXT_SYNC_ID in bytes */
-#define GPIO_IBES_OFFSET 0x1C /* sub-register 0x1C is the GPIO interrupt 揃oth Edge� selection register */
+#define GPIO_IBES_OFFSET 0x1C /* sub-register 0x1C is the GPIO interrupt 揃oth Edge?selection register */
#define GPIO_IBES_LEN (4)
#define GPIO_IBES_MASK GPIO_IRQE_MASK /* */
-#define GIBES0 GIRQx0 /* GPIO IRQ 揃oth Edge� selection for GPIO0 input. Value 0 = GPIO_IMODE register selects the edge. Value 1 = Both edges trigger the interrupt. */
+#define GIBES0 GIRQx0 /* GPIO IRQ 揃oth Edge?selection for GPIO0 input. Value 0 = GPIO_IMODE register selects the edge. Value 1 = Both edges trigger the interrupt. */
#define GIBES1 GIRQx1 /* */
#define GIBES2 GIRQx2 /* */
#define GIBES3 GIRQx3 /* */
@@ -831,20 +831,20 @@
/* offset from DRX_CONF_ID in bytes */
#define DRX_TUNE0b_OFFSET (0x02) /* sub-register 0x02 is a 16-bit tuning register. */
#define DRX_TUNE0b_LEN (2)
-#define DRX_TUNE0b_MASK 0xFFFF /* 7.2.40.2 Sub-Register 0x27:02 � DRX_TUNE0b */
+#define DRX_TUNE0b_MASK 0xFFFF /* 7.2.40.2 Sub-Register 0x27:02 ?DRX_TUNE0b */
/* offset from DRX_CONF_ID in bytes */
-#define DRX_TUNE1a_OFFSET 0x04 /* 7.2.40.3 Sub-Register 0x27:04 � DRX_TUNE1a */
+#define DRX_TUNE1a_OFFSET 0x04 /* 7.2.40.3 Sub-Register 0x27:04 ?DRX_TUNE1a */
#define DRX_TUNE1a_LEN (2)
#define DRX_TUNE1a_MASK 0xFFFF
/* offset from DRX_CONF_ID in bytes */
-#define DRX_TUNE1b_OFFSET 0x06 /* 7.2.40.4 Sub-Register 0x27:06 � DRX_TUNE1b */
+#define DRX_TUNE1b_OFFSET 0x06 /* 7.2.40.4 Sub-Register 0x27:06 ?DRX_TUNE1b */
#define DRX_TUNE1b_LEN (2)
#define DRX_TUNE1b_MASK 0xFFFF
/* offset from DRX_CONF_ID in bytes */
-#define DRX_TUNE2_OFFSET 0x08 /* 7.2.40.5 Sub-Register 0x27:08 � DRX_TUNE2 */
+#define DRX_TUNE2_OFFSET 0x08 /* 7.2.40.5 Sub-Register 0x27:08 ?DRX_TUNE2 */
#define DRX_TUNE2_LEN (4)
#define DRX_TUNE2_MASK 0xFFFFFFFFUL
@@ -852,17 +852,17 @@
/* WARNING: Please do NOT set DRX_SFDTOC to zero (disabling SFD detection timeout)
* since this risks IC malfunction due to prolonged receiver activity in the event of false preamble detection.
*/
-#define DRX_SFDTOC_OFFSET 0x20 /* 7.2.40.7 Sub-Register 0x27:20 � DRX_SFDTOC */
+#define DRX_SFDTOC_OFFSET 0x20 /* 7.2.40.7 Sub-Register 0x27:20 ?DRX_SFDTOC */
#define DRX_SFDTOC_LEN (2)
#define DRX_SFDTOC_MASK 0xFFFF
/* offset from DRX_CONF_ID in bytes */
-#define DRX_PRETOC_OFFSET 0x24 /* 7.2.40.9 Sub-Register 0x27:24 � DRX_PRETOC */
+#define DRX_PRETOC_OFFSET 0x24 /* 7.2.40.9 Sub-Register 0x27:24 ?DRX_PRETOC */
#define DRX_PRETOC_LEN (2)
#define DRX_PRETOC_MASK 0xFFFF
/* offset from DRX_CONF_ID in bytes */
-#define DRX_DRX_TUNE4HOFFSET 0x26 /* 7.2.40.10 Sub-Register 0x27:26 � DRX_TUNE4H */
+#define DRX_DRX_TUNE4HOFFSET 0x26 /* 7.2.40.10 Sub-Register 0x27:26 ?DRX_TUNE4H */
#define DRX_DRX_TUNE4H_LEN (2)
#define DRX_DRX_TUNE4H_MASK 0xFFFF
@@ -871,7 +871,7 @@
/****************************************************************************//**
* @brief Bit definitions for register RF_CONF
* Analog RF Configuration block
- * Refer to section 7.2.41 Register file: 0x28 � Analog RF configuration block
+ * Refer to section 7.2.41 Register file: 0x28 ?Analog RF configuration block
**/
#define RF_CONF_ID 0x28 /* Analog RF Configuration */
#define RF_CONF_LEN (58)
@@ -889,12 +889,12 @@
#define RF_TXCTRL_LEN (4)
#define RF_TXCTRL_TXMTUNE_MASK 0x000001E0UL /* Transmit mixer tuning register */
#define RF_TXCTRL_TXTXMQ_MASK 0x00000E00UL /* Transmit mixer Q-factor tuning register */
-#define RF_TXCTRL_CH1 0x00005C40UL /* 32-bit value to program to Sub-Register 0x28:0C � RF_TXCTRL */
-#define RF_TXCTRL_CH2 0x00045CA0UL /* 32-bit value to program to Sub-Register 0x28:0C � RF_TXCTRL */
-#define RF_TXCTRL_CH3 0x00086CC0UL /* 32-bit value to program to Sub-Register 0x28:0C � RF_TXCTRL */
-#define RF_TXCTRL_CH4 0x00045C80UL /* 32-bit value to program to Sub-Register 0x28:0C � RF_TXCTRL */
-#define RF_TXCTRL_CH5 0x001E3FE0UL /* 32-bit value to program to Sub-Register 0x28:0C � RF_TXCTRL */
-#define RF_TXCTRL_CH7 0x001E7DE0UL /* 32-bit value to program to Sub-Register 0x28:0C � RF_TXCTRL */
+#define RF_TXCTRL_CH1 0x00005C40UL /* 32-bit value to program to Sub-Register 0x28:0C ?RF_TXCTRL */
+#define RF_TXCTRL_CH2 0x00045CA0UL /* 32-bit value to program to Sub-Register 0x28:0C ?RF_TXCTRL */
+#define RF_TXCTRL_CH3 0x00086CC0UL /* 32-bit value to program to Sub-Register 0x28:0C ?RF_TXCTRL */
+#define RF_TXCTRL_CH4 0x00045C80UL /* 32-bit value to program to Sub-Register 0x28:0C ?RF_TXCTRL */
+#define RF_TXCTRL_CH5 0x001E3FE0UL /* 32-bit value to program to Sub-Register 0x28:0C ?RF_TXCTRL */
+#define RF_TXCTRL_CH7 0x001E7DE0UL /* 32-bit value to program to Sub-Register 0x28:0C ?RF_TXCTRL */
/* offset from TX_CAL_ID in bytes */
#define RF_STATUS_OFFSET 0x2C /* */
@@ -909,24 +909,24 @@
/****************************************************************************//**
* @brief Bit definitions for register TX_CAL
- * Refer to section 7.2.43 Register file: 0x2A � Transmitter Calibration block
+ * Refer to section 7.2.43 Register file: 0x2A ?Transmitter Calibration block
**/
#define TX_CAL_ID 0x2A /* Transmitter calibration block */
#define TX_CAL_LEN (52)
/* offset from TX_CAL_ID in bytes */
#define TC_SARL_SAR_C (0) /* SAR control */
-//#define TC_SARL_OFFSET 0x03 /* Transmitter Calibration � Latest SAR readings. RO */
+//#define TC_SARL_OFFSET 0x03 /* Transmitter Calibration ?Latest SAR readings. RO */
//#define TC_SARL_LEN (2)
/*cause bug in register block TX_CAL, we need to read 1 byte in a time*/
#define TC_SARL_SAR_LVBAT_OFFSET (3) /* Latest SAR reading for Voltage level */
#define TC_SARL_SAR_LTEMP_OFFSET (4) /* Latest SAR reading for Temperature level */
/* offset from TX_CAL_ID in bytes */
-//#define TC_SARW_OFFSET 0x06 /* Transmitter Calibration � SAR readings at last Wake-Up */
+//#define TC_SARW_OFFSET 0x06 /* Transmitter Calibration ?SAR readings at last Wake-Up */
//#define TC_SARW_LEN (2)
#define TC_SARW_SAR_WTEMP_OFFSET 0x06 /* SAR reading of Temperature level taken at last wakeup event */
#define TC_SARW_SAR_WVBAT_OFFSET 0x07 /* SAR reading of Voltage level taken at last wakeup event */
/* offset from TX_CAL_ID in bytes */
-#define TC_PGDELAY_OFFSET 0x0B /* Transmitter Calibration � Pulse Generator Delay */
+#define TC_PGDELAY_OFFSET 0x0B /* Transmitter Calibration ?Pulse Generator Delay */
#define TC_PGDELAY_LEN (1)
#define TC_PGDELAY_CH1 0xC9 /* Recommended value for channel 1 */
#define TC_PGDELAY_CH2 0xC2 /* Recommended value for channel 2 */
@@ -935,14 +935,14 @@
#define TC_PGDELAY_CH5 0xC0 /* Recommended value for channel 5 */
#define TC_PGDELAY_CH7 0x93 /* Recommended value for channel 7 */
/* offset from TX_CAL_ID in bytes */
-#define TC_PGTEST_OFFSET 0x0C /* Transmitter Calibration � Pulse Generator Test */
+#define TC_PGTEST_OFFSET 0x0C /* Transmitter Calibration ?Pulse Generator Test */
#define TC_PGTEST_LEN (1)
#define TC_PGTEST_NORMAL 0x00 /* Normal operation */
#define TC_PGTEST_CW 0x13 /* Continuous Wave (CW) Test Mode */
/****************************************************************************//**
* @brief Bit definitions for register
- * Refer to section 7.2.44 Register file: 0x2B � Frequency synthesiser control block
+ * Refer to section 7.2.44 Register file: 0x2B ?Frequency synthesiser control block
**/
#define FS_CTRL_ID 0x2B /* Frequency synthesiser control block */
#define FS_CTRL_LEN (21)
@@ -950,7 +950,7 @@
#define FS_RES1_OFFSET 0x00 /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */
#define FS_RES1_LEN (7)
/* offset from FS_CTRL_ID in bytes */
-#define FS_PLLCFG_OFFSET 0x07 /* Frequency synthesiser � PLL configuration */
+#define FS_PLLCFG_OFFSET 0x07 /* Frequency synthesiser ?PLL configuration */
#define FS_PLLCFG_LEN (5)
#define FS_PLLCFG_CH1 0x09000407UL /* Operating Channel 1 */
#define FS_PLLCFG_CH2 0x08400508UL /* Operating Channel 2 (same as 4) */
@@ -959,7 +959,7 @@
#define FS_PLLCFG_CH5 0x0800041DUL /* Operating Channel 5 (same as 7) */
#define FS_PLLCFG_CH7 0x0800041DUL /* Operating Channel 7 (same as 5) */
/* offset from FS_CTRL_ID in bytes */
-#define FS_PLLTUNE_OFFSET 0x0B /* Frequency synthesiser � PLL Tuning */
+#define FS_PLLTUNE_OFFSET 0x0B /* Frequency synthesiser ?PLL Tuning */
#define FS_PLLTUNE_LEN (1)
#define FS_PLLTUNE_CH1 0x1E /* Operating Channel 1 */
#define FS_PLLTUNE_CH2 0x26 /* Operating Channel 2 (same as 4) */
@@ -971,9 +971,9 @@
#define FS_RES2_OFFSET 0x0C /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */
#define FS_RES2_LEN (2)
/* offset from FS_CTRL_ID in bytes */
-#define FS_XTALT_OFFSET 0x0E /* Frequency synthesiser � Crystal trim */
+#define FS_XTALT_OFFSET 0x0E /* Frequency synthesiser ?Crystal trim */
#define FS_XTALT_LEN (1)
-#define FS_XTALT_MASK 0x1F /* Crystal Trim. Crystals may be trimmed using this register setting to tune out errors, see 8.1 � IC Calibration � Crystal Oscillator Trim. */
+#define FS_XTALT_MASK 0x1F /* Crystal Trim. Crystals may be trimmed using this register setting to tune out errors, see 8.1 ?IC Calibration ?Crystal Oscillator Trim. */
#define FS_XTALT_MIDRANGE 0x10
/* offset from FS_CTRL_ID in bytes */
#define FS_RES3_OFFSET 0x0F /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */
@@ -990,7 +990,7 @@
#define AON_WCFG_MASK 0x09CB /* access mask to AON_WCFG register*/
#define AON_WCFG_ONW_RADC 0x0001 /* On Wake-up Run the (temperature and voltage) Analog-to-Digital Convertors */
#define AON_WCFG_ONW_RX 0x0002 /* On Wake-up turn on the Receiver */
-#define AON_WCFG_ONW_LEUI 0x0008 /* On Wake-up load the EUI from OTP memory into Register file: 0x01 � Extended Unique Identifier. */
+#define AON_WCFG_ONW_LEUI 0x0008 /* On Wake-up load the EUI from OTP memory into Register file: 0x01 ?Extended Unique Identifier. */
#define AON_WCFG_ONW_LDC 0x0040 /* On Wake-up load configurations from the AON memory into the host interface register set */
#define AON_WCFG_ONW_L64P 0x0080 /* On Wake-up load the Length64 receiver operating parameter set */
#define AON_WCFG_PRES_SLEEP 0x0100 /* Preserve Sleep. This bit determines what the DW1000 does with respect to the ARXSLP and ATXSLP sleep controls */
@@ -1034,7 +1034,7 @@
/****************************************************************************//**
* @brief Bit definitions for register OTP_IF
- * Refer to section 7.2.46 Register file: 0x2D � OTP Memory Interface
+ * Refer to section 7.2.46 Register file: 0x2D ?OTP Memory Interface
**/
#define OTP_IF_ID 0x2D /* One Time Programmable Memory Interface */
#define OTP_IF_LEN (18)
@@ -1076,8 +1076,8 @@
/****************************************************************************//**
* @brief Bit definitions for register LDE_IF
- * Refer to section 7.2.47 Register file: 0x2E � Leading Edge Detection Interface
- * PLEASE NOTE: Other areas within the address space of Register file: 0x2E � Leading Edge Detection Interface
+ * Refer to section 7.2.47 Register file: 0x2E ?Leading Edge Detection Interface
+ * PLEASE NOTE: Other areas within the address space of Register file: 0x2E ?Leading Edge Detection Interface
* are reserved. To ensure proper operation of the LDE algorithm (i.e. to avoid loss of performance or a malfunction),
* care must be taken not to write to any byte locations other than those defined in the sub-sections below.
**/
@@ -1168,11 +1168,11 @@
#define EVC_TXFS_MASK 0x0FFF
/* offset from DIG_DIAG_ID in bytes */
-#define EVC_HPW_OFFSET 0x18 /* The EVC_HPW field is a 12-bit counter of 揌alf Period Warnings�. */
+#define EVC_HPW_OFFSET 0x18 /* The EVC_HPW field is a 12-bit counter of 揌alf Period Warnings? */
#define EVC_HPW_LEN (2)
#define EVC_HPW_MASK 0x0FFF
/* offset from DIG_DIAG_ID in bytes */
-#define EVC_TPW_OFFSET 0x1A /* The EVC_TPW field is a 12-bit counter of 揟ransmitter Power-Up Warnings�. */
+#define EVC_TPW_OFFSET 0x1A /* The EVC_TPW field is a 12-bit counter of 揟ransmitter Power-Up Warnings? */
#define EVC_TPW_LEN (2)
#define EVC_TPW_MASK 0x0FFF
@@ -1243,7 +1243,7 @@
#define PMSC_RES3_OFFSET 0x24
/* offset from PMSC_ID in bytes */
#define PMSC_TXFINESEQ_OFFSET 0x26 /* Writing PMSC_TXFINESEQ_DIS_MASK disables fine grain sequencing in the transmitter*/
-#define PMSC_TXFINESEQ_DIS_MASK (0x0)
+#define PMSC_TXFINESEQ_DIS_MASK (0x0)
#define PMSC_TXFINESEQ_EN_MASK (0B74) /* Writing PMSC_TXFINESEQ_EN_MASK enables fine grain sequencing in the transmitter*/
/* offset from PMSC_ID in bytes */
#define PMSC_LEDC_OFFSET 0x28
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c"
index 640c1b3..20697f8 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c"
@@ -32,7 +32,8 @@
#define RNG_DELAY_MS 100
/* Default communication configuration. We use here EVK1000's default mode (mode 3). */
-static dwt_config_t config = {
+static dwt_config_t config =
+{
2, /* Channel number. */
DWT_PRF_64M, /* Pulse repetition frequency. */
DWT_PLEN_1024, /* Preamble length. */
@@ -51,7 +52,7 @@
static uint8 tx_resp_msg[] = {0x41, 0x88, 0, 0xCA, 0xDE, 'V', 'E', 'W', 'A', 0x10, 0x02, 0, 0, 0, 0};
static uint8 rx_final_msg[] = {0x41, 0x88, 0, 0xCA, 0xDE, 'W', 'A', 'V', 'E', 0x23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-
+
/* Frames used in the ranging process. See NOTE 2 below. */
static uint8 tx_poll_msg[] = {0x00, 0x88, 0, 0xCA, 0xDE, 'W', 'A', 'V', 'E', 0x21, 0, 0};
static uint8 rx_resp_msg[] = {0x41, 0x88, 0, 0xCA, 0xDE, 'V', 'E', 'W', 'A', 0x10, 0x02, 0, 0, 0, 0};
@@ -64,7 +65,7 @@
static uint64 final_rx_ts;
static double tof;
-static double distance,dist2;
+static double distance, dist2;
int16_t dist[8];
#define ALL_MSG_COMMON_LEN 10
/* Indexes to access some of the fields in the frames defined above. */
@@ -80,7 +81,7 @@
* Its size is adjusted to longest frame that this example code is supposed to handle. */
#define RX_BUF_LEN 20
#define RX_BUF_LEN2 24
-static uint8 rx_buffer[RX_BUF_LEN+4];
+static uint8 rx_buffer[RX_BUF_LEN + 4];
/* Hold copy of status register state here for reference, so reader can examine it at a breakpoint. */
static uint32 status_reg = 0;
@@ -125,7 +126,7 @@
*
* @return none
*/
- static void final_msg_get_ts(const uint8 *ts_field, uint32 *ts)
+static void final_msg_get_ts(const uint8 *ts_field, uint32 *ts)
{
int i;
*ts = 0;
@@ -134,67 +135,67 @@
*ts += ts_field[i] << (i * 8);
}
}
- void GPIO_Toggle(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+void GPIO_Toggle(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
- GPIO_WriteBit(GPIOx, GPIO_Pin, (BitAction)!GPIO_ReadOutputDataBit(GPIOx, GPIO_Pin));
+ GPIO_WriteBit(GPIOx, GPIO_Pin, (BitAction)!GPIO_ReadOutputDataBit(GPIOx, GPIO_Pin));
}
int fputc(int ch, FILE *f)
{
-USART_SendData(USART1, (unsigned char) ch);// USART1 ???? USART2 ?
+ USART_SendData(USART1, (unsigned char) ch);// USART1 ???? USART2 ?
-while (!(USART1->SR & USART_FLAG_TXE));
+ while (!(USART1->SR & USART_FLAG_TXE));
-return (ch);
+ return (ch);
}
void USART_putc(char c)
{
- //while(!(USART2->SR & 0x00000040));
- //USART_SendData(USART2,c);
- /* e.g. write a character to the USART */
- USART_SendData(USART1, c);
+ //while(!(USART2->SR & 0x00000040));
+ //USART_SendData(USART2,c);
+ /* e.g. write a character to the USART */
+ USART_SendData(USART1, c);
- /* Loop until the end of transmission */
- while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) ;
+ /* Loop until the end of transmission */
+ while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) ;
}
-void USART_puts(uint8_t *s,uint8_t len)
+void USART_puts(uint8_t *s, uint8_t len)
{
- int i;
- for(i=0; i<len; i++)
- {
- USART_putc(s[i]);
- }
+ int i;
+ for(i = 0; i < len; i++)
+ {
+ USART_putc(s[i]);
+ }
}
int ld[100];
-int LP(int tmp,uint8_t channel)
+int LP(int tmp, uint8_t channel)
{
-int data;
- data = 0.7*ld[channel]+0.3*tmp;
- ld[channel]=data;
- return data;
+ int data;
+ data = 0.7 * ld[channel] + 0.3 * tmp;
+ ld[channel] = data;
+ return data;
}
-uint16_t Checksum_u16(uint8_t* pdata, uint32_t len)
+uint16_t Checksum_u16(uint8_t *pdata, uint32_t len)
{
uint16_t sum = 0;
uint32_t i;
- for(i=0; i<len; i++)
+ for(i = 0; i < len; i++)
sum += pdata[i];
sum = ~sum;
return sum;
}
void LED_blink(void)
{
- uint8_t ii;
- for (ii=0;ii<10;ii++)
-{
- GPIO_Toggle(GPIOA,LED_PIN);
- deca_sleep(100);
-}
+ uint8_t ii;
+ for (ii = 0; ii < 10; ii++)
+ {
+ GPIO_Toggle(GPIOA, LED_PIN);
+ deca_sleep(100);
+ }
}
extern volatile unsigned long time32_reset;
extern uint8_t Work_Mode;
@@ -203,16 +204,16 @@
char dist_str[16] = {0};
int32_t dis;
double dID;
-uint8_t TAG_ID,ANCHOR_ID, jumptime=0;
-uint32_t rec_dist,hex_dist;
+uint8_t TAG_ID, ANCHOR_ID, jumptime = 0;
+uint32_t rec_dist, hex_dist;
uint16_t check;
int main(void)
{
- RCC_ClocksTypeDef RCC_Clocks; /* Start with board specific hardware init. */
+ RCC_ClocksTypeDef RCC_Clocks; /* Start with board specific hardware init. */
peripherals_init();//初始化外设
-RCC_GetClocksFreq(&RCC_Clocks);
+ RCC_GetClocksFreq(&RCC_Clocks);
/* Display application name on LCD. */
- // lcd_display_str(APP_NAME);
+ // lcd_display_str(APP_NAME);
/* Reset and initialise DW1000.
* For initialisation, DW1000 clocks must be temporarily set to crystal speed. After initialisation SPI rate can be increased for optimum
@@ -234,275 +235,283 @@
dwt_setrxaftertxdelay(POLL_TX_TO_RESP_RX_DLY_UUS);//设置发送后开启接收，并设定延迟时间
dwt_setrxtimeout(RESP_RX_TIMEOUT_UUS); //设置接收超时时间
- send[0]=0x6D; //串口数据
- send[1]=0xD6; //串口数据
+ send[0] = 0x6D; //串口数据
+ send[1] = 0xD6; //串口数据
- tx_poll_msg[6] = ANCHOR_ID; //UWB POLL 包数据
- rx_resp_msg[6] = ANCHOR_ID; //UWB RESPONSE 包数据
- tx_final_msg[6] = ANCHOR_ID;//UWB Fianl 包数据
-
- rx_poll_msg[6] = ANCHOR_ID;
- tx_resp_msg[6] = ANCHOR_ID;
- rx_final_msg[6] = ANCHOR_ID;
-
- tx_poll_msg[5] = TAG_ID;//UWB POLL 包数据
- rx_resp_msg[5] = TAG_ID;//UWB RESPONSE 包数据
- tx_final_msg[5] = TAG_ID;//UWB Fianl 包数据
+ tx_poll_msg[6] = ANCHOR_ID; //UWB POLL 包数据
+ rx_resp_msg[6] = ANCHOR_ID; //UWB RESPONSE 包数据
+ tx_final_msg[6] = ANCHOR_ID;//UWB Fianl 包数据
+
+ rx_poll_msg[6] = ANCHOR_ID;
+ tx_resp_msg[6] = ANCHOR_ID;
+ rx_final_msg[6] = ANCHOR_ID;
+
+ tx_poll_msg[5] = TAG_ID;//UWB POLL 包数据
+ rx_resp_msg[5] = TAG_ID;//UWB RESPONSE 包数据
+ tx_final_msg[5] = TAG_ID;//UWB Fianl 包数据
/* Loop forever initiating ranging exchanges. */
- LED_blink();
- if(!Work_Mode) //选择发送模式（TAG标签）还是接收模式(ANCHOR基站)
- {
- while (1) //发送模式(TAG标签)
+ LED_blink();
+ if(!Work_Mode) //选择发送模式（TAG标签）还是接收模式(ANCHOR基站)
{
- /* Write frame data to DW1000 and prepare transmission. See NOTE 7 below. */
- tx_poll_msg[ALL_MSG_SN_IDX] = frame_seq_nb;
- dwt_writetxdata(sizeof(tx_poll_msg), tx_poll_msg, 0);//将Poll包数据传给DW1000，将在开启发送时传出去
- dwt_writetxfctrl(sizeof(tx_poll_msg), 0);//设置超宽带发送数据长度
-
- /* Start transmission, indicating that a response is expected so that reception is enabled automatically after the frame is sent and the delay
- * set by dwt_setrxaftertxdelay() has elapsed. */
- dwt_starttx(DWT_START_TX_IMMEDIATE | DWT_RESPONSE_EXPECTED);//开启发送，发送完成后等待一段时间开启接收，等待时间在dwt_setrxaftertxdelay中设置
-
- /* We assume that the transmission is achieved correctly, poll for reception of a frame or error/timeout. See NOTE 8 below. */
- while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG | SYS_STATUS_ALL_RX_ERR)))//不断查询芯片状态直到成功接收或者发生错误
- { };
-
- /* Increment frame sequence number after transmission of the poll message (modulo 256). */
- frame_seq_nb++;
-
- if (status_reg & SYS_STATUS_RXFCG)//如果成功接收
+ while (1) //发送模式(TAG标签)
{
- uint32 frame_len;
+ /* Write frame data to DW1000 and prepare transmission. See NOTE 7 below. */
+ tx_poll_msg[ALL_MSG_SN_IDX] = frame_seq_nb;
+ dwt_writetxdata(sizeof(tx_poll_msg), tx_poll_msg, 0);//将Poll包数据传给DW1000，将在开启发送时传出去
+ dwt_writetxfctrl(sizeof(tx_poll_msg), 0);//设置超宽带发送数据长度
- /* Clear good RX frame event and TX frame sent in the DW1000 status register. */
- dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXFCG | SYS_STATUS_TXFRS);//清楚寄存器标志位
+ /* Start transmission, indicating that a response is expected so that reception is enabled automatically after the frame is sent and the delay
+ * set by dwt_setrxaftertxdelay() has elapsed. */
+ dwt_starttx(DWT_START_TX_IMMEDIATE | DWT_RESPONSE_EXPECTED);//开启发送，发送完成后等待一段时间开启接收，等待时间在dwt_setrxaftertxdelay中设置
- /* A frame has been received, read it into the local buffer. */
- frame_len = dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXFLEN_MASK; //获得接收到的数据长度
+ /* We assume that the transmission is achieved correctly, poll for reception of a frame or error/timeout. See NOTE 8 below. */
+ while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG | SYS_STATUS_ALL_RX_ERR)))//不断查询芯片状态直到成功接收或者发生错误
+ { };
+
+ /* Increment frame sequence number after transmission of the poll message (modulo 256). */
+ frame_seq_nb++;
+
+ if (status_reg & SYS_STATUS_RXFCG)//如果成功接收
+ {
+ uint32 frame_len;
+
+ /* Clear good RX frame event and TX frame sent in the DW1000 status register. */
+ dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXFCG | SYS_STATUS_TXFRS);//清楚寄存器标志位
+
+ /* A frame has been received, read it into the local buffer. */
+ frame_len = dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXFLEN_MASK; //获得接收到的数据长度
dwt_readrxdata(rx_buffer, frame_len, 0); //读取接收数据
- /* Check that the frame is the expected response from the companion "DS TWR responder" example.
- * As the sequence number field of the frame is not relevant, it is cleared to simplify the validation of the frame. */
- rx_buffer[ALL_MSG_SN_IDX] = 0;
- if (rx_buffer[9]==0x10)//判断接收到的数据是否是response数据
- {
- uint32 final_tx_time;
-
-
- /* Retrieve poll transmission and response reception timestamp. */
- poll_tx_ts = get_tx_timestamp_u64(); //获得POLL发送时间T1
- resp_rx_ts = get_rx_timestamp_u64(); //获得RESPONSE接收时间T4
-
- memcpy(&dist[TAG_ID],&rx_buffer[11],2);
-
- /* Compute final message transmission time. See NOTE 9 below. */
- final_tx_time = (resp_rx_ts + (RESP_RX_TO_FINAL_TX_DLY_UUS * UUS_TO_DWT_TIME)) >> 8;//计算final包发送时间，T5=T4+Treply2
- dwt_setdelayedtrxtime(final_tx_time);//设置final包发送时间T5
-
- /* Final TX timestamp is the transmission time we programmed plus the TX antenna delay. */
- final_tx_ts = (((uint64)(final_tx_time & 0xFFFFFFFE)) << 8) + TX_ANT_DLY;//final包实际发送时间是计算时间加上发送天线delay
-
- /* Write all timestamps in the final message. See NOTE 10 below. */
- final_msg_set_ts(&tx_final_msg[FINAL_MSG_POLL_TX_TS_IDX], poll_tx_ts);//将T1，T4，T5写入发送数据
- final_msg_set_ts(&tx_final_msg[FINAL_MSG_RESP_RX_TS_IDX], resp_rx_ts);
- final_msg_set_ts(&tx_final_msg[FINAL_MSG_FINAL_TX_TS_IDX], final_tx_ts);
-
- /* Write and send final message. See NOTE 7 below. */
- tx_final_msg[ALL_MSG_SN_IDX] = frame_seq_nb;
- dwt_writetxdata(sizeof(tx_final_msg), tx_final_msg, 0);//将发送数据写入DW1000
- dwt_writetxfctrl(sizeof(tx_final_msg), 0);//设定发送数据长度
- dwt_starttx(DWT_START_TX_DELAYED);//设定为延迟发送
-
- if (GPIO_ReadInputDataBit(GPIOA,SW2) != RESET) //通过拨码开关判断数据输出格式
- {
- dID=TAG_ID;
- printf("TAG_ID: %2.0f ", dID);
- dID=ANCHOR_ID;
- printf("ANCHOR_ID: %2.0f ", dID);
- printf("Distance: %5.0f cm\n", (double)dist[TAG_ID]);
- }else{
- send[2] = ANCHOR_ID;
- send[3] = TAG_ID;
-
- memcpy(&send[4],&dist[TAG_ID],2);
- check=Checksum_u16(&send[2],6);
- memcpy(&send[8],&check,2);
- USART_puts(send,10);
- }
- /* Poll DW1000 until TX frame sent event set. See NOTE 8 below. */
- while (!(dwt_read32bitreg(SYS_STATUS_ID) & SYS_STATUS_TXFRS))//不断查询芯片状态直到发送完成
- { };
-
- /* Clear TXFRS event. */
- dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_TXFRS);//清楚标志位
-
- /* Increment frame sequence number after transmission of the final message (modulo 256). */
- frame_seq_nb++;
- time32_reset = 0;
- GPIO_Toggle(GPIOA,LED_PIN);//LED闪烁
- jumptime = 0;
- }else{
- jumptime =5;//如果通讯失败，将间隔时间增加5ms，避开因为多标签同时发送引起的冲突。
- }
- }
- else
- {
- /* Clear RX error events in the DW1000 status register. */
- dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR);
- jumptime =5;
- }
-
- /* Execute a delay between ranging exchanges. */
- deca_sleep(RNG_DELAY_MS+jumptime);//休眠固定时间
- }
- }else{
- while (1)//接收模式(ANCHOR基站)
- {
- /* Clear reception timeout to start next ranging process. */
- dwt_setrxtimeout(0);//设定接收超时时间，0位没有超时时间
-
- /* Activate reception immediately. */
- dwt_rxenable(0);//打开接收
-
- /* Poll for reception of a frame or error/timeout. See NOTE 7 below. */
- while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG | SYS_STATUS_ALL_RX_ERR)))//不断查询芯片状态直到接收成功或者出现错误
- { };
-
- if (status_reg & SYS_STATUS_RXFCG)//成功接收
- {
-
-
- /* Clear good RX frame event in the DW1000 status register. */
- dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXFCG);//清楚标志位
-
- /* A frame has been received, read it into the local buffer. */
- frame_len = dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXFL_MASK_1023;//获得接收数据长度
-
- dwt_readrxdata(rx_buffer, frame_len, 0);//读取接收数据
-
-
- /* Check that the frame is a poll sent by "DS TWR initiator" example.
- * As the sequence number field of the frame is not relevant, it is cleared to simplify the validation of the frame. */
- rx_buffer[ALL_MSG_SN_IDX] = 0;
- TAG_ID = rx_buffer[5];
- rx_poll_msg[5] = TAG_ID;//为多标签通讯服务，防止一次通讯中接收到不同ID标签的数据
- tx_resp_msg[5] = TAG_ID;
- rx_final_msg[5] = TAG_ID;
- if (rx_buffer[9]==0x21)//判断是否是poll包数据
- {
- uint32 resp_tx_time;
-
- /* Retrieve poll reception timestamp. */
- poll_rx_ts = get_rx_timestamp_u64();//获得Poll包接收时间T2
-
- /* Set send time for response. See NOTE 8 below. */
- resp_tx_time = (poll_rx_ts + (POLL_RX_TO_RESP_TX_DLY_UUS * UUS_TO_DWT_TIME)) >> 8;//计算Response发送时间T3。
- dwt_setdelayedtrxtime(resp_tx_time);//设置Response发送时间T3
-
- /* Set expected delay and timeout for final message reception. */
- dwt_setrxaftertxdelay(RESP_TX_TO_FINAL_RX_DLY_UUS);//设置发送完成后开启接收延迟时间
- dwt_setrxtimeout(FINAL_RX_TIMEOUT_UUS);//接收超时时间
-
- /* Write and send the response message. See NOTE 9 below.*/
- memcpy(&tx_resp_msg[11],&dist[TAG_ID],2);
- tx_resp_msg[ALL_MSG_SN_IDX] = frame_seq_nb;
- dwt_writetxdata(sizeof(tx_resp_msg), tx_resp_msg, 0);//写入发送数据
- dwt_writetxfctrl(sizeof(tx_resp_msg), 0);//设定发送长度
- dwt_starttx(DWT_START_TX_DELAYED | DWT_RESPONSE_EXPECTED);//延迟发送，等待接收
-
- /* We assume that the transmission is achieved correctly, now poll for reception of expected "final" frame or error/timeout.
- * See NOTE 7 below. */
- while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG | SYS_STATUS_ALL_RX_ERR)))///不断查询芯片状态直到接收成功或者出现错误
- { };
-
- /* Increment frame sequence number after transmission of the response message (modulo 256). */
- frame_seq_nb++;
-
- if (status_reg & SYS_STATUS_RXFCG)//接收成功
+ /* Check that the frame is the expected response from the companion "DS TWR responder" example.
+ * As the sequence number field of the frame is not relevant, it is cleared to simplify the validation of the frame. */
+ rx_buffer[ALL_MSG_SN_IDX] = 0;
+ if (rx_buffer[9] == 0x10) //判断接收到的数据是否是response数据
{
- /* Clear good RX frame event and TX frame sent in the DW1000 status register. */
- dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXFCG | SYS_STATUS_TXFRS);//清楚标志位
+ uint32 final_tx_time;
- /* A frame has been received, read it into the local buffer. */
- frame_len = dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXFLEN_MASK;//数据长度
- dwt_readrxdata(rx_buffer, frame_len, 0);//读取接收数据
-
+ /* Retrieve poll transmission and response reception timestamp. */
+ poll_tx_ts = get_tx_timestamp_u64(); //获得POLL发送时间T1
+ resp_rx_ts = get_rx_timestamp_u64(); //获得RESPONSE接收时间T4
- /* Check that the frame is a final message sent by "DS TWR initiator" example.
- * As the sequence number field of the frame is not used in this example, it can be zeroed to ease the validation of the frame. */
- rx_buffer[ALL_MSG_SN_IDX] = 0;
- if (rx_buffer[9]==0x23)//判断是否为Fianl包
+ memcpy(&dist[TAG_ID], &rx_buffer[11], 2);
+
+ /* Compute final message transmission time. See NOTE 9 below. */
+ final_tx_time = (resp_rx_ts + (RESP_RX_TO_FINAL_TX_DLY_UUS * UUS_TO_DWT_TIME)) >> 8;//计算final包发送时间，T5=T4+Treply2
+ dwt_setdelayedtrxtime(final_tx_time);//设置final包发送时间T5
+
+ /* Final TX timestamp is the transmission time we programmed plus the TX antenna delay. */
+ final_tx_ts = (((uint64)(final_tx_time & 0xFFFFFFFE)) << 8) + TX_ANT_DLY;//final包实际发送时间是计算时间加上发送天线delay
+
+ /* Write all timestamps in the final message. See NOTE 10 below. */
+ final_msg_set_ts(&tx_final_msg[FINAL_MSG_POLL_TX_TS_IDX], poll_tx_ts);//将T1，T4，T5写入发送数据
+ final_msg_set_ts(&tx_final_msg[FINAL_MSG_RESP_RX_TS_IDX], resp_rx_ts);
+ final_msg_set_ts(&tx_final_msg[FINAL_MSG_FINAL_TX_TS_IDX], final_tx_ts);
+
+ /* Write and send final message. See NOTE 7 below. */
+ tx_final_msg[ALL_MSG_SN_IDX] = frame_seq_nb;
+ dwt_writetxdata(sizeof(tx_final_msg), tx_final_msg, 0);//将发送数据写入DW1000
+ dwt_writetxfctrl(sizeof(tx_final_msg), 0);//设定发送数据长度
+ dwt_starttx(DWT_START_TX_DELAYED);//设定为延迟发送
+
+ if (GPIO_ReadInputDataBit(GPIOA, SW2) != RESET) //通过拨码开关判断数据输出格式
{
- uint32 poll_tx_ts, resp_rx_ts, final_tx_ts;
- uint32 poll_rx_ts_32, resp_tx_ts_32, final_rx_ts_32;
- double Ra, Rb, Da, Db;
- int64 tof_dtu;
-
- /* Retrieve response transmission and final reception timestamps. */
- resp_tx_ts = get_tx_timestamp_u64();//获得response发送时间T3
- final_rx_ts = get_rx_timestamp_u64();//获得final接收时间T6
-
- /* Get timestamps embedded in the final message. */
- final_msg_get_ts(&rx_buffer[FINAL_MSG_POLL_TX_TS_IDX], &poll_tx_ts);//从接收数据中读取T1，T4，T5
- final_msg_get_ts(&rx_buffer[FINAL_MSG_RESP_RX_TS_IDX], &resp_rx_ts);
- final_msg_get_ts(&rx_buffer[FINAL_MSG_FINAL_TX_TS_IDX], &final_tx_ts);
-
- /* Compute time of flight. 32-bit subtractions give correct answers even if clock has wrapped. See NOTE 10 below. */
- poll_rx_ts_32 = (uint32)poll_rx_ts;//使用32位数据计算
- resp_tx_ts_32 = (uint32)resp_tx_ts;
- final_rx_ts_32 = (uint32)final_rx_ts;
- Ra = (double)(resp_rx_ts - poll_tx_ts);//Tround1 = T4 - T1
- Rb = (double)(final_rx_ts_32 - resp_tx_ts_32);//Tround2 = T6 - T3
- Da = (double)(final_tx_ts - resp_rx_ts);//Treply2 = T5 - T4
- Db = (double)(resp_tx_ts_32 - poll_rx_ts_32);//Treply1 = T3 - T2
- tof_dtu = (int64)((Ra * Rb - Da * Db) / (Ra + Rb + Da + Db));//计算公式
-
- tof = tof_dtu * DWT_TIME_UNITS;
- distance = tof * SPEED_OF_LIGHT;//距离=光速*飞行时间
- dist2 = distance - dwt_getrangebias(config.chan,(float)distance, config.prf);//距离减去矫正系数
-
- dis = dist2*100;//dis 为单位为cm的距离
- dist[TAG_ID] = LP(dis,TAG_ID);//LP 为低通滤波器，让数据更稳定
- time32_reset = 0;
- GPIO_Toggle(GPIOA,LED_PIN);
- if (GPIO_ReadInputDataBit(GPIOA,SW2) != RESET) //通过拨码开关判断数据输出格式
- {
- dID=TAG_ID;
- printf("TAG_ID: %2.0f ", dID);
- dID=ANCHOR_ID;
- printf("ANCHOR_ID: %2.0f ", dID);
+ dID = TAG_ID;
+ printf("TAG_ID: %2.0f ", dID);
+ dID = ANCHOR_ID;
+ printf("ANCHOR_ID: %2.0f ", dID);
printf("Distance: %5.0f cm\n", (double)dist[TAG_ID]);
- }else{
- send[2] = ANCHOR_ID;
- send[3] = TAG_ID;
-
- memcpy(&send[4],&dist[TAG_ID],2);
- check=Checksum_u16(&send[2],6);
- memcpy(&send[8],&check,2);
- USART_puts(send,10);
- }
-
}
+ else
+ {
+ send[2] = ANCHOR_ID;
+ send[3] = TAG_ID;
+
+ memcpy(&send[4], &dist[TAG_ID], 2);
+ check = Checksum_u16(&send[2], 6);
+ memcpy(&send[8], &check, 2);
+ USART_puts(send, 10);
+ }
+ /* Poll DW1000 until TX frame sent event set. See NOTE 8 below. */
+ while (!(dwt_read32bitreg(SYS_STATUS_ID) & SYS_STATUS_TXFRS))//不断查询芯片状态直到发送完成
+ { };
+
+ /* Clear TXFRS event. */
+ dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_TXFRS);//清楚标志位
+
+ /* Increment frame sequence number after transmission of the final message (modulo 256). */
+ frame_seq_nb++;
+ time32_reset = 0;
+ GPIO_Toggle(GPIOA, LED_PIN); //LED闪烁
+ jumptime = 0;
}
else
{
- /* Clear RX error events in the DW1000 status register. */
- dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR);
+ jumptime = 5; //如果通讯失败，将间隔时间增加5ms，避开因为多标签同时发送引起的冲突。
}
}
- }
- else
- {
- /* Clear RX error events in the DW1000 status register. */
- dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR);
+ else
+ {
+ /* Clear RX error events in the DW1000 status register. */
+ dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR);
+ jumptime = 5;
+ }
+
+ /* Execute a delay between ranging exchanges. */
+ deca_sleep(RNG_DELAY_MS + jumptime); //休眠固定时间
}
}
-
-
- }
+ else
+ {
+ while (1)//接收模式(ANCHOR基站)
+ {
+ /* Clear reception timeout to start next ranging process. */
+ dwt_setrxtimeout(0);//设定接收超时时间，0位没有超时时间
+
+ /* Activate reception immediately. */
+ dwt_rxenable(0);//打开接收
+
+ /* Poll for reception of a frame or error/timeout. See NOTE 7 below. */
+ while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG | SYS_STATUS_ALL_RX_ERR)))//不断查询芯片状态直到接收成功或者出现错误
+ { };
+
+ if (status_reg & SYS_STATUS_RXFCG)//成功接收
+ {
+
+
+ /* Clear good RX frame event in the DW1000 status register. */
+ dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXFCG);//清楚标志位
+
+ /* A frame has been received, read it into the local buffer. */
+ frame_len = dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXFL_MASK_1023;//获得接收数据长度
+
+ dwt_readrxdata(rx_buffer, frame_len, 0);//读取接收数据
+
+
+ /* Check that the frame is a poll sent by "DS TWR initiator" example.
+ * As the sequence number field of the frame is not relevant, it is cleared to simplify the validation of the frame. */
+ rx_buffer[ALL_MSG_SN_IDX] = 0;
+ TAG_ID = rx_buffer[5];
+ rx_poll_msg[5] = TAG_ID;//为多标签通讯服务，防止一次通讯中接收到不同ID标签的数据
+ tx_resp_msg[5] = TAG_ID;
+ rx_final_msg[5] = TAG_ID;
+ if (rx_buffer[9] == 0x21) //判断是否是poll包数据
+ {
+ uint32 resp_tx_time;
+
+ /* Retrieve poll reception timestamp. */
+ poll_rx_ts = get_rx_timestamp_u64();//获得Poll包接收时间T2
+
+ /* Set send time for response. See NOTE 8 below. */
+ resp_tx_time = (poll_rx_ts + (POLL_RX_TO_RESP_TX_DLY_UUS * UUS_TO_DWT_TIME)) >> 8;//计算Response发送时间T3。
+ dwt_setdelayedtrxtime(resp_tx_time);//设置Response发送时间T3
+
+ /* Set expected delay and timeout for final message reception. */
+ dwt_setrxaftertxdelay(RESP_TX_TO_FINAL_RX_DLY_UUS);//设置发送完成后开启接收延迟时间
+ dwt_setrxtimeout(FINAL_RX_TIMEOUT_UUS);//接收超时时间
+
+ /* Write and send the response message. See NOTE 9 below.*/
+ memcpy(&tx_resp_msg[11], &dist[TAG_ID], 2);
+ tx_resp_msg[ALL_MSG_SN_IDX] = frame_seq_nb;
+ dwt_writetxdata(sizeof(tx_resp_msg), tx_resp_msg, 0);//写入发送数据
+ dwt_writetxfctrl(sizeof(tx_resp_msg), 0);//设定发送长度
+ dwt_starttx(DWT_START_TX_DELAYED | DWT_RESPONSE_EXPECTED);//延迟发送，等待接收
+
+ /* We assume that the transmission is achieved correctly, now poll for reception of expected "final" frame or error/timeout.
+ * See NOTE 7 below. */
+ while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG | SYS_STATUS_ALL_RX_ERR)))///不断查询芯片状态直到接收成功或者出现错误
+ { };
+
+ /* Increment frame sequence number after transmission of the response message (modulo 256). */
+ frame_seq_nb++;
+
+ if (status_reg & SYS_STATUS_RXFCG)//接收成功
+ {
+ /* Clear good RX frame event and TX frame sent in the DW1000 status register. */
+ dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXFCG | SYS_STATUS_TXFRS);//清楚标志位
+
+ /* A frame has been received, read it into the local buffer. */
+ frame_len = dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXFLEN_MASK;//数据长度
+
+ dwt_readrxdata(rx_buffer, frame_len, 0);//读取接收数据
+
+
+ /* Check that the frame is a final message sent by "DS TWR initiator" example.
+ * As the sequence number field of the frame is not used in this example, it can be zeroed to ease the validation of the frame. */
+ rx_buffer[ALL_MSG_SN_IDX] = 0;
+ if (rx_buffer[9] == 0x23) //判断是否为Fianl包
+ {
+ uint32 poll_tx_ts, resp_rx_ts, final_tx_ts;
+ uint32 poll_rx_ts_32, resp_tx_ts_32, final_rx_ts_32;
+ double Ra, Rb, Da, Db;
+ int64 tof_dtu;
+
+ /* Retrieve response transmission and final reception timestamps. */
+ resp_tx_ts = get_tx_timestamp_u64();//获得response发送时间T3
+ final_rx_ts = get_rx_timestamp_u64();//获得final接收时间T6
+
+ /* Get timestamps embedded in the final message. */
+ final_msg_get_ts(&rx_buffer[FINAL_MSG_POLL_TX_TS_IDX], &poll_tx_ts);//从接收数据中读取T1，T4，T5
+ final_msg_get_ts(&rx_buffer[FINAL_MSG_RESP_RX_TS_IDX], &resp_rx_ts);
+ final_msg_get_ts(&rx_buffer[FINAL_MSG_FINAL_TX_TS_IDX], &final_tx_ts);
+
+ /* Compute time of flight. 32-bit subtractions give correct answers even if clock has wrapped. See NOTE 10 below. */
+ poll_rx_ts_32 = (uint32)poll_rx_ts;//使用32位数据计算
+ resp_tx_ts_32 = (uint32)resp_tx_ts;
+ final_rx_ts_32 = (uint32)final_rx_ts;
+ Ra = (double)(resp_rx_ts - poll_tx_ts);//Tround1 = T4 - T1
+ Rb = (double)(final_rx_ts_32 - resp_tx_ts_32);//Tround2 = T6 - T3
+ Da = (double)(final_tx_ts - resp_rx_ts);//Treply2 = T5 - T4
+ Db = (double)(resp_tx_ts_32 - poll_rx_ts_32);//Treply1 = T3 - T2
+ tof_dtu = (int64)((Ra * Rb - Da * Db) / (Ra + Rb + Da + Db));//计算公式
+
+ tof = tof_dtu * DWT_TIME_UNITS;
+ distance = tof * SPEED_OF_LIGHT;//距离=光速*飞行时间
+ dist2 = distance - dwt_getrangebias(config.chan, (float)distance, config.prf); //距离减去矫正系数
+
+ dis = dist2 * 100; //dis 为单位为cm的距离
+ dist[TAG_ID] = LP(dis, TAG_ID); //LP 为低通滤波器，让数据更稳定
+ time32_reset = 0;
+ GPIO_Toggle(GPIOA, LED_PIN);
+ if (GPIO_ReadInputDataBit(GPIOA, SW2) != RESET) //通过拨码开关判断数据输出格式
+ {
+ dID = TAG_ID;
+ printf("TAG_ID: %2.0f ", dID);
+ dID = ANCHOR_ID;
+ printf("ANCHOR_ID: %2.0f ", dID);
+ printf("Distance: %5.0f cm\n", (double)dist[TAG_ID]);
+ }
+ else
+ {
+ send[2] = ANCHOR_ID;
+ send[3] = TAG_ID;
+
+ memcpy(&send[4], &dist[TAG_ID], 2);
+ check = Checksum_u16(&send[2], 6);
+ memcpy(&send[8], &check, 2);
+ USART_puts(send, 10);
+ }
+
+ }
+ }
+ else
+ {
+ /* Clear RX error events in the DW1000 status register. */
+ dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR);
+ }
+ }
+ }
+ else
+ {
+ /* Clear RX error events in the DW1000 status register. */
+ dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR);
+ }
+ }
+
+
+ }
}
/*! ------------------------------------------------------------------------------------------------------------------
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_mutex.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_mutex.c"
index 841f26c..1c742cc 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_mutex.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_mutex.c"
@@ -14,14 +14,14 @@
#include "port.h"
// ---------------------------------------------------------------------------
//
-// NB: The purpose of this file is to provide for microprocessor interrupt enable/disable, this is used for
-// controlling mutual exclusion from critical sections in the code where interrupts and background
-// processing may interact. The code using this is kept to a minimum and the disabling time is also
+// NB: The purpose of this file is to provide for microprocessor interrupt enable/disable, this is used for
+// controlling mutual exclusion from critical sections in the code where interrupts and background
+// processing may interact. The code using this is kept to a minimum and the disabling time is also
// kept to a minimum, so blanket interrupt disable may be the easiest way to provide this. But at a
// minimum those interrupts coming from the decawave device should be disabled/re-enabled by this activity.
//
// In porting this to a particular microprocessor, the implementer may choose to use #defines in the
-// deca_irq.h include file to map these calls transparently to the target system. Alternatively the
+// deca_irq.h include file to map these calls transparently to the target system. Alternatively the
// appropriate code may be embedded in the functions provided below.
//
// This mutex dependent on HW port.
@@ -42,31 +42,32 @@
*
* Note: The body of this function is defined in deca_mutex.c and is platform specific
*
- * input parameters:
+ * input parameters:
*
* output parameters
*
* returns the state of the DW1000 interrupt
*/
-decaIrqStatus_t decamutexon(void)
+decaIrqStatus_t decamutexon(void)
{
- decaIrqStatus_t s = port_GetEXT_IRQStatus();
+ decaIrqStatus_t s = port_GetEXT_IRQStatus();
- if(s) {
- port_DisableEXT_IRQ(); //disable the external interrupt line
- }
- return s ; // return state before disable, value is used to re-enable in decamutexoff call
+ if(s)
+ {
+ port_DisableEXT_IRQ(); //disable the external interrupt line
+ }
+ return s ; // return state before disable, value is used to re-enable in decamutexoff call
}
/*! ------------------------------------------------------------------------------------------------------------------
* Function: decamutexoff()
*
- * Description: This function should re-enable interrupts, or at least restore their state as returned(&saved) by decamutexon
+ * Description: This function should re-enable interrupts, or at least restore their state as returned(&saved) by decamutexon
* This is called at the end of a critical section
*
* Note: The body of this function is defined in deca_mutex.c and is platform specific
*
- * input parameters:
+ * input parameters:
* @param s - the state of the DW1000 interrupt as returned by decamutexon
*
* output parameters
@@ -75,7 +76,8 @@
*/
void decamutexoff(decaIrqStatus_t s) // put a function here that re-enables the interrupt at the end of the critical section
{
- if(s) { //need to check the port state as we can't use level sensitive interrupt on the STM ARM
- port_EnableEXT_IRQ();
- }
+ if(s) //need to check the port state as we can't use level sensitive interrupt on the STM ARM
+ {
+ port_EnableEXT_IRQ();
+ }
}
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_spi.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_spi.c"
index 0a165e8..d54ac60 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_spi.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/deca_spi.c"
@@ -19,15 +19,15 @@
int writetospi_serial( uint16_t headerLength,
- const uint8_t *headerBuffer,
- uint32_t bodylength,
- const uint8_t *bodyBuffer
- );
+ const uint8_t *headerBuffer,
+ uint32_t bodylength,
+ const uint8_t *bodyBuffer
+ );
int readfromspi_serial( uint16_t headerLength,
- const uint8_t *headerBuffer,
- uint32_t readlength,
- uint8_t *readBuffer );
+ const uint8_t *headerBuffer,
+ uint32_t readlength,
+ uint8_t *readBuffer );
/*! ------------------------------------------------------------------------------------------------------------------
* Function: openspi()
*
@@ -36,9 +36,9 @@
*/
int openspi(/*SPI_TypeDef* SPIx*/)
{
- // done by port.c, default SPI used is SPI1
+ // done by port.c, default SPI used is SPI1
- return 0;
+ return 0;
} // end openspi()
@@ -50,11 +50,11 @@
*/
int closespi(void)
{
- while (port_SPIx_busy_sending()); //wait for tx buffer to empty
+ while (port_SPIx_busy_sending()); //wait for tx buffer to empty
- port_SPIx_disable();
+ port_SPIx_disable();
- return 0;
+ return 0;
} // end closespi()
@@ -75,7 +75,7 @@
)
{
- int i=0;
+ int i = 0;
decaIrqStatus_t stat ;
@@ -83,23 +83,23 @@
SPIx_CS_GPIO->BRR = SPIx_CS;
- for(i=0; i<headerLength; i++)
+ for(i = 0; i < headerLength; i++)
{
- SPIx->DR = headerBuffer[i];
+ SPIx->DR = headerBuffer[i];
- while ((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
+ while ((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
- SPIx->DR ;
+ SPIx->DR ;
}
- for(i=0; i<bodylength; i++)
+ for(i = 0; i < bodylength; i++)
{
- SPIx->DR = bodyBuffer[i];
+ SPIx->DR = bodyBuffer[i];
- while((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
+ while((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
- SPIx->DR ;
- }
+ SPIx->DR ;
+ }
SPIx_CS_GPIO->BSRR = SPIx_CS;
@@ -127,7 +127,7 @@
)
{
- int i=0;
+ int i = 0;
decaIrqStatus_t stat ;
@@ -138,22 +138,22 @@
SPIx_CS_GPIO->BRR = SPIx_CS;
- for(i=0; i<headerLength; i++)
+ for(i = 0; i < headerLength; i++)
{
- SPIx->DR = headerBuffer[i];
+ SPIx->DR = headerBuffer[i];
- while((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
+ while((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
- readBuffer[0] = SPIx->DR ; // Dummy read as we write the header
+ readBuffer[0] = SPIx->DR ; // Dummy read as we write the header
}
- for(i=0; i<readlength; i++)
+ for(i = 0; i < readlength; i++)
{
- SPIx->DR = 0; // Dummy write as we read the message body
+ SPIx->DR = 0; // Dummy write as we read the message body
- while((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
-
- readBuffer[i] = SPIx->DR ;//port_SPIx_receive_data(); //this clears RXNE bit
+ while((SPIx->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET);
+
+ readBuffer[i] = SPIx->DR ;//port_SPIx_receive_data(); //this clears RXNE bit
}
SPIx_CS_GPIO->BSRR = SPIx_CS;
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/lcd.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/lcd.c"
index 00a8f8b..dd56657 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/lcd.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/lcd.c"
@@ -30,44 +30,44 @@
int sleep = 0;
//int j = 10000;
-// if(rs_enable)
-// {
-// port_LCD_RS_set();
-// }
-// else
-// {
-// if(bodylength == 1)
-// {
-// if(bodyBuffer[0] & 0x3) //if this is command = 1 or 2 - exsecution time is > 1ms
-// sleep = 1 ;
-// }
-// port_LCD_RS_clear();
-// }
+ // if(rs_enable)
+ // {
+ // port_LCD_RS_set();
+ // }
+ // else
+ // {
+ // if(bodylength == 1)
+ // {
+ // if(bodyBuffer[0] & 0x3) //if this is command = 1 or 2 - exsecution time is > 1ms
+ // sleep = 1 ;
+ // }
+ // port_LCD_RS_clear();
+ // }
-// port_SPIy_clear_chip_select(); //CS low
+ // port_SPIy_clear_chip_select(); //CS low
-// //while(j--); //delay
+ // //while(j--); //delay
-// for(i=0; i<bodylength; i++)
-// {
-// port_SPIy_send_data(bodyBuffer[i]); //send data on the SPI
+ // for(i=0; i<bodylength; i++)
+ // {
+ // port_SPIy_send_data(bodyBuffer[i]); //send data on the SPI
-// while (port_SPIy_no_data()); //wait for rx buffer to fill
+ // while (port_SPIy_no_data()); //wait for rx buffer to fill
-// port_SPIy_receive_data(); //this clears RXNE bit
-// }
+ // port_SPIy_receive_data(); //this clears RXNE bit
+ // }
-// //j = 10000;
+ // //j = 10000;
-// port_LCD_RS_clear();
+ // port_LCD_RS_clear();
-// //while(j--); //delay
+ // //while(j--); //delay
-// port_SPIy_set_chip_select(); //CS high
+ // port_SPIy_set_chip_select(); //CS high
-// if(sleep)
-// deca_sleep(2);
+ // if(sleep)
+ // deca_sleep(2);
} // end writetoLCD()
/*! ------------------------------------------------------------------------------------------------------------------
@@ -84,12 +84,12 @@
{
uint8 command;
/* Return cursor home and clear screen. */
-// command = 0x2;
-// writetoLCD(1, 0, &command);
-// command = 0x1;
-// writetoLCD(1, 0, &command);
-// /* Write the string to display. */
-// writetoLCD(strlen(string), 1, (const uint8 *)string);
+ // command = 0x2;
+ // writetoLCD(1, 0, &command);
+ // command = 0x1;
+ // writetoLCD(1, 0, &command);
+ // /* Write the string to display. */
+ // writetoLCD(strlen(string), 1, (const uint8 *)string);
}
#endif
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.c"
index 87806f8..c9b87fc 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.c"
@@ -36,124 +36,124 @@
int No_Configuration(void)
{
- return -1;
+ return -1;
}
unsigned long portGetTickCnt(void)
{
- return time32_incr;
+ return time32_incr;
}
int SysTick_Configuration(void)
{
- if (SysTick_Config(SystemCoreClock / CLOCKS_PER_SEC))
- {
- /* Capture error */
- while (1);
- }
- NVIC_SetPriority (SysTick_IRQn, 5);
+ if (SysTick_Config(SystemCoreClock / CLOCKS_PER_SEC))
+ {
+ /* Capture error */
+ while (1);
+ }
+ NVIC_SetPriority (SysTick_IRQn, 5);
- return 0;
+ return 0;
}
void RTC_Configuration(void)
{
- /* Enable PWR and BKP clocks */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
+ /* Enable PWR and BKP clocks */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
- /* Allow access to BKP Domain */
- PWR_BackupAccessCmd(ENABLE);
+ /* Allow access to BKP Domain */
+ PWR_BackupAccessCmd(ENABLE);
- /* Reset Backup Domain */
- BKP_DeInit();
+ /* Reset Backup Domain */
+ BKP_DeInit();
- /* Enable LSE */
- RCC_LSEConfig(RCC_LSE_ON);
- /* Wait till LSE is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET){}
+ /* Enable LSE */
+ RCC_LSEConfig(RCC_LSE_ON);
+ /* Wait till LSE is ready */
+ while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) {}
- /* Select LSE as RTC Clock Source */
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+ /* Select LSE as RTC Clock Source */
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
- /* Enable RTC Clock */
- RCC_RTCCLKCmd(ENABLE);
+ /* Enable RTC Clock */
+ RCC_RTCCLKCmd(ENABLE);
- /* Wait for RTC registers synchronization */
- RTC_WaitForSynchro();
+ /* Wait for RTC registers synchronization */
+ RTC_WaitForSynchro();
- /* Wait until last write operation on RTC registers has finished */
- RTC_WaitForLastTask();
+ /* Wait until last write operation on RTC registers has finished */
+ RTC_WaitForLastTask();
- /* Enable the RTC Second */
- RTC_ITConfig(RTC_IT_SEC, ENABLE);
+ /* Enable the RTC Second */
+ RTC_ITConfig(RTC_IT_SEC, ENABLE);
- /* Wait until last write operation on RTC registers has finished */
- RTC_WaitForLastTask();
+ /* Wait until last write operation on RTC registers has finished */
+ RTC_WaitForLastTask();
- /* Set RTC prescaler: set RTC period to 1sec */
- RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
+ /* Set RTC prescaler: set RTC period to 1sec */
+ RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
- /* Wait until last write operation on RTC registers has finished */
- RTC_WaitForLastTask();
+ /* Wait until last write operation on RTC registers has finished */
+ RTC_WaitForLastTask();
}
int NVIC_DisableDECAIRQ(void)
{
- EXTI_InitTypeDef EXTI_InitStructure;
+ EXTI_InitTypeDef EXTI_InitStructure;
- /* Configure EXTI line */
- EXTI_InitStructure.EXTI_Line = DECAIRQ_EXTI;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MPW3 IRQ polarity is high by default
- EXTI_InitStructure.EXTI_LineCmd = DECAIRQ_EXTI_NOIRQ;
- EXTI_Init(&EXTI_InitStructure);
+ /* Configure EXTI line */
+ EXTI_InitStructure.EXTI_Line = DECAIRQ_EXTI;
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MPW3 IRQ polarity is high by default
+ EXTI_InitStructure.EXTI_LineCmd = DECAIRQ_EXTI_NOIRQ;
+ EXTI_Init(&EXTI_InitStructure);
- return 0;
+ return 0;
}
int NVIC_Configuration(void)
{
- GPIO_InitTypeDef GPIO_InitStructure;
- EXTI_InitTypeDef EXTI_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
+ EXTI_InitTypeDef EXTI_InitStructure;
+ NVIC_InitTypeDef NVIC_InitStructure;
- // Enable GPIO used as DECA IRQ for interrupt
- GPIO_InitStructure.GPIO_Pin = DECAIRQ;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; //IRQ pin should be Pull Down to prevent unnecessary EXT IRQ while DW1000 goes to sleep mode
- GPIO_Init(DECAIRQ_GPIO, &GPIO_InitStructure);
+ // Enable GPIO used as DECA IRQ for interrupt
+ GPIO_InitStructure.GPIO_Pin = DECAIRQ;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; //IRQ pin should be Pull Down to prevent unnecessary EXT IRQ while DW1000 goes to sleep mode
+ GPIO_Init(DECAIRQ_GPIO, &GPIO_InitStructure);
- /* Connect EXTI Line to GPIO Pin */
- GPIO_EXTILineConfig(DECAIRQ_EXTI_PORT, DECAIRQ_EXTI_PIN);
+ /* Connect EXTI Line to GPIO Pin */
+ GPIO_EXTILineConfig(DECAIRQ_EXTI_PORT, DECAIRQ_EXTI_PIN);
- /* Configure EXTI line */
- EXTI_InitStructure.EXTI_Line = DECAIRQ_EXTI;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MPW3 IRQ polarity is high by default
- EXTI_InitStructure.EXTI_LineCmd = DECAIRQ_EXTI_USEIRQ;
- EXTI_Init(&EXTI_InitStructure);
+ /* Configure EXTI line */
+ EXTI_InitStructure.EXTI_Line = DECAIRQ_EXTI;
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MPW3 IRQ polarity is high by default
+ EXTI_InitStructure.EXTI_LineCmd = DECAIRQ_EXTI_USEIRQ;
+ EXTI_Init(&EXTI_InitStructure);
- /* Set NVIC Grouping to 16 groups of interrupt without sub-grouping */
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
+ /* Set NVIC Grouping to 16 groups of interrupt without sub-grouping */
+ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
- /* Enable and set EXTI Interrupt to the lowest priority */
- NVIC_InitStructure.NVIC_IRQChannel = DECAIRQ_EXTI_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 15;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = DECAIRQ_EXTI_USEIRQ;
+ /* Enable and set EXTI Interrupt to the lowest priority */
+ NVIC_InitStructure.NVIC_IRQChannel = DECAIRQ_EXTI_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 15;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = DECAIRQ_EXTI_USEIRQ;
- NVIC_Init(&NVIC_InitStructure);
+ NVIC_Init(&NVIC_InitStructure);
- /* Enable the RTC Interrupt */
- //NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
- //NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 10;
- //NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- //NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ /* Enable the RTC Interrupt */
+ //NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
+ //NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 10;
+ //NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ //NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- //NVIC_Init(&NVIC_InitStructure);
+ //NVIC_Init(&NVIC_InitStructure);
- return 0;
+ return 0;
}
/**
@@ -165,137 +165,137 @@
*/
ITStatus EXTI_GetITEnStatus(uint32_t EXTI_Line)
{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
- enablestatus = EXTI->IMR & EXTI_Line;
- if (enablestatus != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
+ enablestatus = EXTI->IMR & EXTI_Line;
+ if (enablestatus != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
}
int RCC_Configuration(void)
{
- ErrorStatus HSEStartUpStatus;
- RCC_ClocksTypeDef RCC_ClockFreq;
+ ErrorStatus HSEStartUpStatus;
+ RCC_ClocksTypeDef RCC_ClockFreq;
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- // select HSI as PLL source
- RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC_HSI_Div2;
-
- //PLLCLK=8/2*12=48M
- RCC->CFGR |= (uint32_t)RCC_CFGR_PLLMULL9;
-
- /* HCLK = SYSCLK/1 */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- SystemCoreClockUpdate();
- RCC_GetClocksFreq(&RCC_ClockFreq);
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
- /* Enable SPI1 clock */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+ // select HSI as PLL source
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC_HSI_Div2;
- /* Enable SPI2 clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+ //PLLCLK=8/2*12=48M
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PLLMULL9;
- /* Enable GPIOs clocks */
- RCC_APB2PeriphClockCmd(
- RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
- RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD |
- RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO,
- ENABLE);
+ /* HCLK = SYSCLK/1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
- return 0;
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ SystemCoreClockUpdate();
+ RCC_GetClocksFreq(&RCC_ClockFreq);
+
+ /* Enable SPI1 clock */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+
+ /* Enable SPI2 clock */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+
+ /* Enable GPIOs clocks */
+ RCC_APB2PeriphClockCmd(
+ RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
+ RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD |
+ RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO,
+ ENABLE);
+
+ return 0;
}
void usartinit(void)
{
- USART_InitTypeDef USART_InitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
+ USART_InitTypeDef USART_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
- /* USARTx configured as follow:
- - BaudRate = 115200 baud
- - Word Length = 8 Bits
- - One Stop Bit
- - No parity
- - Hardware flow control disabled (RTS and CTS signals)
- - Receive and transmit enabled
- */
- USART_InitStructure.USART_BaudRate = 115200 ;
- USART_InitStructure.USART_WordLength = USART_WordLength_8b;
- USART_InitStructure.USART_StopBits = USART_StopBits_1;
- USART_InitStructure.USART_Parity = USART_Parity_No;
- USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ /* USARTx configured as follow:
+ - BaudRate = 115200 baud
+ - Word Length = 8 Bits
+ - One Stop Bit
+ - No parity
+ - Hardware flow control disabled (RTS and CTS signals)
+ - Receive and transmit enabled
+ */
+ USART_InitStructure.USART_BaudRate = 115200 ;
+ USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+ USART_InitStructure.USART_StopBits = USART_StopBits_1;
+ USART_InitStructure.USART_Parity = USART_Parity_No;
+ USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+ USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- /* Enable GPIO clock */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);
+ /* Enable GPIO clock */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);
- //For EVB1000 -> USART2_REMAP = 0
+ //For EVB1000 -> USART2_REMAP = 0
- /* Enable the USART2 Pins Software Remapping */
+ /* Enable the USART2 Pins Software Remapping */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
- /* Configure USART Tx as alternate function push-pull */
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
+ /* Configure USART Tx as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
- /* Configure USART Rx as input floating */
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
+ /* Configure USART Rx as input floating */
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
- /* USART configuration */
- USART_Init(USART1, &USART_InitStructure);
+ /* USART configuration */
+ USART_Init(USART1, &USART_InitStructure);
- /* Enable USART */
- USART_Cmd(USART1, ENABLE);
+ /* Enable USART */
+ USART_Cmd(USART1, ENABLE);
}
void SPI_ChangeRate(uint16_t scalingfactor)
{
- uint16_t tmpreg = 0;
+ uint16_t tmpreg = 0;
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
- /*clear the scaling bits*/
- tmpreg &= 0xFFC7;
+ /*clear the scaling bits*/
+ tmpreg &= 0xFFC7;
- /*set the scaling bits*/
- tmpreg |= scalingfactor;
+ /*set the scaling bits*/
+ tmpreg |= scalingfactor;
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -328,83 +328,83 @@
void SPI_ConfigFastRate(uint16_t scalingfactor)
{
- SPI_InitTypeDef SPI_InitStructure;
+ SPI_InitTypeDef SPI_InitStructure;
- SPI_I2S_DeInit(SPIx);
+ SPI_I2S_DeInit(SPIx);
- // SPIx Mode setup
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
- SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
- SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; //
- //SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //
- SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
- //SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //
- //SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
- SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
- SPI_InitStructure.SPI_BaudRatePrescaler = scalingfactor; //sets BR[2:0] bits - baudrate in SPI_CR1 reg bits 4-6
- SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
- SPI_InitStructure.SPI_CRCPolynomial = 7;
+ // SPIx Mode setup
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; //
+ //SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+ //SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //
+ //SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ SPI_InitStructure.SPI_BaudRatePrescaler = scalingfactor; //sets BR[2:0] bits - baudrate in SPI_CR1 reg bits 4-6
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_InitStructure.SPI_CRCPolynomial = 7;
- SPI_Init(SPIx, &SPI_InitStructure);
+ SPI_Init(SPIx, &SPI_InitStructure);
- // Enable SPIx
- SPI_Cmd(SPIx, ENABLE);
+ // Enable SPIx
+ SPI_Cmd(SPIx, ENABLE);
}
int SPI_Configuration(void)
{
- SPI_InitTypeDef SPI_InitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
+ SPI_InitTypeDef SPI_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
- SPI_I2S_DeInit(SPIx);
+ SPI_I2S_DeInit(SPIx);
- // SPIx Mode setup
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
- SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
- SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; //
- //SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //
- SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
- //SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //
- //SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
- SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
- //SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; //sets BR[2:0] bits - baudrate in SPI_CR1 reg bits 4-6
- SPI_InitStructure.SPI_BaudRatePrescaler = SPIx_PRESCALER;
- SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
- SPI_InitStructure.SPI_CRCPolynomial = 7;
+ // SPIx Mode setup
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; //
+ //SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+ //SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //
+ //SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ //SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; //sets BR[2:0] bits - baudrate in SPI_CR1 reg bits 4-6
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPIx_PRESCALER;
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_InitStructure.SPI_CRCPolynomial = 7;
- SPI_Init(SPIx, &SPI_InitStructure);
+ SPI_Init(SPIx, &SPI_InitStructure);
- // SPIx SCK and MOSI pin setup
- GPIO_InitStructure.GPIO_Pin = SPIx_SCK | SPIx_MOSI;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ // SPIx SCK and MOSI pin setup
+ GPIO_InitStructure.GPIO_Pin = SPIx_SCK | SPIx_MOSI;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPIx_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIx_GPIO, &GPIO_InitStructure);
- // SPIx MISO pin setup
- GPIO_InitStructure.GPIO_Pin = SPIx_MISO;
- //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ // SPIx MISO pin setup
+ GPIO_InitStructure.GPIO_Pin = SPIx_MISO;
+ //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(SPIx_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIx_GPIO, &GPIO_InitStructure);
- // SPIx CS pin setup
- GPIO_InitStructure.GPIO_Pin = SPIx_CS;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ // SPIx CS pin setup
+ GPIO_InitStructure.GPIO_Pin = SPIx_CS;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPIx_CS_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIx_CS_GPIO, &GPIO_InitStructure);
- // Disable SPIx SS Output
- SPI_SSOutputCmd(SPIx, DISABLE);
+ // Disable SPIx SS Output
+ SPI_SSOutputCmd(SPIx, DISABLE);
- // Enable SPIx
- SPI_Cmd(SPIx, ENABLE);
+ // Enable SPIx
+ SPI_Cmd(SPIx, ENABLE);
- // Set CS high
- GPIO_SetBits(SPIx_CS_GPIO, SPIx_CS);
+ // Set CS high
+ GPIO_SetBits(SPIx_CS_GPIO, SPIx_CS);
return 0;
}
@@ -412,71 +412,71 @@
int SPI2_Configuration(void)
{
- SPI_InitTypeDef SPI_InitStructure;
- GPIO_InitTypeDef GPIO_InitStructure;
+ SPI_InitTypeDef SPI_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
- SPI_I2S_DeInit(SPIy);
+ SPI_I2S_DeInit(SPIy);
- // SPIy Mode setup
- //SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
- SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
- //SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; //
- SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //
- //SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
- SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //
- //SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
- SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
- SPI_InitStructure.SPI_BaudRatePrescaler = SPIy_PRESCALER;
- SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
- SPI_InitStructure.SPI_CRCPolynomial = 7;
+ // SPIy Mode setup
+ //SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+ //SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; //
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //
+ //SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //
+ //SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPIy_PRESCALER;
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_InitStructure.SPI_CRCPolynomial = 7;
- SPI_Init(SPIy, &SPI_InitStructure);
+ SPI_Init(SPIy, &SPI_InitStructure);
- // SPIy SCK and MOSI pin setup
- GPIO_InitStructure.GPIO_Pin = SPIy_SCK | SPIy_MOSI;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ // SPIy SCK and MOSI pin setup
+ GPIO_InitStructure.GPIO_Pin = SPIy_SCK | SPIy_MOSI;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
- // SPIy MISO pin setup
- GPIO_InitStructure.GPIO_Pin = SPIy_MISO;
- //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ // SPIy MISO pin setup
+ GPIO_InitStructure.GPIO_Pin = SPIy_MISO;
+ //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
- // SPIy CS pin setup
- GPIO_InitStructure.GPIO_Pin = SPIy_CS;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ // SPIy CS pin setup
+ GPIO_InitStructure.GPIO_Pin = SPIy_CS;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPIy_CS_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIy_CS_GPIO, &GPIO_InitStructure);
- // Disable SPIy SS Output
- SPI_SSOutputCmd(SPIy, DISABLE);
+ // Disable SPIy SS Output
+ SPI_SSOutputCmd(SPIy, DISABLE);
- // Enable SPIy
- SPI_Cmd(SPIy, ENABLE);
+ // Enable SPIy
+ SPI_Cmd(SPIy, ENABLE);
- // Set CS high
- GPIO_SetBits(SPIy_CS_GPIO, SPIy_CS);
+ // Set CS high
+ GPIO_SetBits(SPIy_CS_GPIO, SPIy_CS);
- // LCD_RS pin setup
- GPIO_InitStructure.GPIO_Pin = LCD_RS;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ // LCD_RS pin setup
+ GPIO_InitStructure.GPIO_Pin = LCD_RS;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
- // LCD_RW pin setup
- GPIO_InitStructure.GPIO_Pin = LCD_RW;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ // LCD_RW pin setup
+ GPIO_InitStructure.GPIO_Pin = LCD_RW;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
+ GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
return 0;
}
@@ -490,90 +490,92 @@
#define SW7 GPIO_Pin_7
#define SW8 GPIO_Pin_8
uint8_t Work_Mode;
-extern uint8_t TAG_ID,ANCHOR_ID;
+extern uint8_t TAG_ID, ANCHOR_ID;
int GPIO_Configuration(void)
{
- GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
- /* Configure all unused GPIO port pins in Analog Input mode (floating input
- * trigger OFF), this will reduce the power consumption and increase the device
- * immunity against EMI/EMC */
+ /* Configure all unused GPIO port pins in Analog Input mode (floating input
+ * trigger OFF), this will reduce the power consumption and increase the device
+ * immunity against EMI/EMC */
- // Enable GPIOs clocks
- RCC_APB2PeriphClockCmd(
- RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
- RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO,
- ENABLE);
+ // Enable GPIOs clocks
+ RCC_APB2PeriphClockCmd(
+ RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
+ RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO,
+ ENABLE);
- // Set all GPIO pins as analog inputs
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_Init(GPIOB, &GPIO_InitStructure);
- GPIO_Init(GPIOC, &GPIO_InitStructure);
+ // Set all GPIO pins as analog inputs
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
-GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
- //Enable GPIO used for User button
- GPIO_InitStructure.GPIO_Pin = TA_BOOT1;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_Init(TA_BOOT1_GPIO, &GPIO_InitStructure);
+ GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
+ //Enable GPIO used for User button
+ GPIO_InitStructure.GPIO_Pin = TA_BOOT1;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(TA_BOOT1_GPIO, &GPIO_InitStructure);
- //Enable GPIO used for Response Delay setting
-
- GPIO_InitStructure.GPIO_Pin = SW1|SW2;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- GPIO_InitStructure.GPIO_Pin = SW3 | SW4 | SW5 | SW6 | SW7 | SW8;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
-
- GPIO_InitStructure.GPIO_Pin = LED_PIN;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
+ //Enable GPIO used for Response Delay setting
-if (GPIO_ReadInputDataBit(GPIOA,SW1) == RESET)
-{
- Work_Mode = 0;//TX
- GPIO_Toggle(GPIOA,LED_PIN);
-}else{
- Work_Mode = 1; //RX
-}
- TAG_ID = 0;
-if(GPIO_ReadInputDataBit(GPIOB,SW6) == RESET)
-{
- TAG_ID |= 1<<2;
-}
-if(GPIO_ReadInputDataBit(GPIOB,SW7) == RESET)
-{
- TAG_ID |= 1<<1;
-}
-if(GPIO_ReadInputDataBit(GPIOB,SW8) == RESET)
-{
- TAG_ID |= 1;
-}
+ GPIO_InitStructure.GPIO_Pin = SW1 | SW2;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
-if(GPIO_ReadInputDataBit(GPIOB,SW3) == RESET)
-{
- ANCHOR_ID |= 1<<2;
-}
-if(GPIO_ReadInputDataBit(GPIOB,SW4) == RESET)
-{
- ANCHOR_ID |= 1<<1;
-}
-if(GPIO_ReadInputDataBit(GPIOB,SW5) == RESET)
-{
- ANCHOR_ID |= 1;
-}
+ GPIO_InitStructure.GPIO_Pin = SW3 | SW4 | SW5 | SW6 | SW7 | SW8;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
- // Disable GPIOs clocks
- //RCC_APB2PeriphClockCmd(
- // RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
- // RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD |
- // RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO,
- // DISABLE);
+ GPIO_InitStructure.GPIO_Pin = LED_PIN;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
- // Enable GPIO used for LEDs
+ if (GPIO_ReadInputDataBit(GPIOA, SW1) == RESET)
+ {
+ Work_Mode = 0;//TX
+ GPIO_Toggle(GPIOA, LED_PIN);
+ }
+ else
+ {
+ Work_Mode = 1; //RX
+ }
+ TAG_ID = 0;
+ if(GPIO_ReadInputDataBit(GPIOB, SW6) == RESET)
+ {
+ TAG_ID |= 1 << 2;
+ }
+ if(GPIO_ReadInputDataBit(GPIOB, SW7) == RESET)
+ {
+ TAG_ID |= 1 << 1;
+ }
+ if(GPIO_ReadInputDataBit(GPIOB, SW8) == RESET)
+ {
+ TAG_ID |= 1;
+ }
+
+ if(GPIO_ReadInputDataBit(GPIOB, SW3) == RESET)
+ {
+ ANCHOR_ID |= 1 << 2;
+ }
+ if(GPIO_ReadInputDataBit(GPIOB, SW4) == RESET)
+ {
+ ANCHOR_ID |= 1 << 1;
+ }
+ if(GPIO_ReadInputDataBit(GPIOB, SW5) == RESET)
+ {
+ ANCHOR_ID |= 1;
+ }
+
+ // Disable GPIOs clocks
+ //RCC_APB2PeriphClockCmd(
+ // RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
+ // RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD |
+ // RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO,
+ // DISABLE);
+
+ // Enable GPIO used for LEDs
return 0;
@@ -582,22 +584,22 @@
void reset_DW1000(void)
{
- GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
- // Enable GPIO used for DW1000 reset
- GPIO_InitStructure.GPIO_Pin = DW1000_RSTn;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(DW1000_RSTn_GPIO, &GPIO_InitStructure);
+ // Enable GPIO used for DW1000 reset
+ GPIO_InitStructure.GPIO_Pin = DW1000_RSTn;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(DW1000_RSTn_GPIO, &GPIO_InitStructure);
- //drive the RSTn pin low
- GPIO_ResetBits(DW1000_RSTn_GPIO, DW1000_RSTn);
+ //drive the RSTn pin low
+ GPIO_ResetBits(DW1000_RSTn_GPIO, DW1000_RSTn);
- //put the pin back to tri-state ... as input
- GPIO_InitStructure.GPIO_Pin = DW1000_RSTn;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(DW1000_RSTn_GPIO, &GPIO_InitStructure);
+ //put the pin back to tri-state ... as input
+ GPIO_InitStructure.GPIO_Pin = DW1000_RSTn;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(DW1000_RSTn_GPIO, &GPIO_InitStructure);
deca_sleep(2);
}
@@ -605,214 +607,214 @@
void setup_DW1000RSTnIRQ(int enable)
{
- GPIO_InitTypeDef GPIO_InitStructure;
- EXTI_InitTypeDef EXTI_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
+ EXTI_InitTypeDef EXTI_InitStructure;
+ NVIC_InitTypeDef NVIC_InitStructure;
- if(enable)
- {
- // Enable GPIO used as DECA IRQ for interrupt
- GPIO_InitStructure.GPIO_Pin = DECARSTIRQ;
- //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; //IRQ pin should be Pull Down to prevent unnecessary EXT IRQ while DW1000 goes to sleep mode
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_Init(DECARSTIRQ_GPIO, &GPIO_InitStructure);
+ if(enable)
+ {
+ // Enable GPIO used as DECA IRQ for interrupt
+ GPIO_InitStructure.GPIO_Pin = DECARSTIRQ;
+ //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; //IRQ pin should be Pull Down to prevent unnecessary EXT IRQ while DW1000 goes to sleep mode
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(DECARSTIRQ_GPIO, &GPIO_InitStructure);
- /* Connect EXTI Line to GPIO Pin */
- GPIO_EXTILineConfig(DECARSTIRQ_EXTI_PORT, DECARSTIRQ_EXTI_PIN);
+ /* Connect EXTI Line to GPIO Pin */
+ GPIO_EXTILineConfig(DECARSTIRQ_EXTI_PORT, DECARSTIRQ_EXTI_PIN);
- /* Configure EXTI line */
- EXTI_InitStructure.EXTI_Line = DECARSTIRQ_EXTI;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MP IRQ polarity is high by default
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
+ /* Configure EXTI line */
+ EXTI_InitStructure.EXTI_Line = DECARSTIRQ_EXTI;
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MP IRQ polarity is high by default
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+ EXTI_Init(&EXTI_InitStructure);
- /* Set NVIC Grouping to 16 groups of interrupt without sub-grouping */
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
+ /* Set NVIC Grouping to 16 groups of interrupt without sub-grouping */
+ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
- /* Enable and set EXTI Interrupt to the lowest priority */
- NVIC_InitStructure.NVIC_IRQChannel = DECARSTIRQ_EXTI_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 15;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ /* Enable and set EXTI Interrupt to the lowest priority */
+ NVIC_InitStructure.NVIC_IRQChannel = DECARSTIRQ_EXTI_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 15;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
- }
- else
- {
- //put the pin back to tri-state ... as input
- GPIO_InitStructure.GPIO_Pin = DW1000_RSTn;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(DW1000_RSTn_GPIO, &GPIO_InitStructure);
+ NVIC_Init(&NVIC_InitStructure);
+ }
+ else
+ {
+ //put the pin back to tri-state ... as input
+ GPIO_InitStructure.GPIO_Pin = DW1000_RSTn;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(DW1000_RSTn_GPIO, &GPIO_InitStructure);
- /* Configure EXTI line */
- EXTI_InitStructure.EXTI_Line = DECARSTIRQ_EXTI;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MP IRQ polarity is high by default
- EXTI_InitStructure.EXTI_LineCmd = DISABLE;
- EXTI_Init(&EXTI_InitStructure);
- }
+ /* Configure EXTI line */
+ EXTI_InitStructure.EXTI_Line = DECARSTIRQ_EXTI;
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; //MP IRQ polarity is high by default
+ EXTI_InitStructure.EXTI_LineCmd = DISABLE;
+ EXTI_Init(&EXTI_InitStructure);
+ }
}
int ETH_GPIOConfigure(void)
{
#if 0
- GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
- /* ETHERNET pins configuration */
- /* AF Output Push Pull:
- - ETH_MII_MDIO / ETH_RMII_MDIO: PA2
- - ETH_MII_MDC / ETH_RMII_MDC: PC1
- - ETH_MII_TXD2: PC2
- - ETH_MII_TX_EN / ETH_RMII_TX_EN: PB11
- - ETH_MII_TXD0 / ETH_RMII_TXD0: PB12
- - ETH_MII_TXD1 / ETH_RMII_TXD1: PB13
- - ETH_MII_PPS_OUT / ETH_RMII_PPS_OUT: PB5
- - ETH_MII_TXD3: PB8 */
+ /* ETHERNET pins configuration */
+ /* AF Output Push Pull:
+ - ETH_MII_MDIO / ETH_RMII_MDIO: PA2
+ - ETH_MII_MDC / ETH_RMII_MDC: PC1
+ - ETH_MII_TXD2: PC2
+ - ETH_MII_TX_EN / ETH_RMII_TX_EN: PB11
+ - ETH_MII_TXD0 / ETH_RMII_TXD0: PB12
+ - ETH_MII_TXD1 / ETH_RMII_TXD1: PB13
+ - ETH_MII_PPS_OUT / ETH_RMII_PPS_OUT: PB5
+ - ETH_MII_TXD3: PB8 */
- /* Configure PA2 as alternate function push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
+ /* Configure PA2 as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
- /* Configure PC1 and PC2 as alternate function push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_Init(GPIOC, &GPIO_InitStructure);
+ /* Configure PC1 and PC2 as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
- /* Configure PB5, PB8, PB11, PB12 and PB13 as alternate function push-pull */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 |
- GPIO_Pin_12 | GPIO_Pin_13;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
+ /* Configure PB5, PB8, PB11, PB12 and PB13 as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 |
+ GPIO_Pin_12 | GPIO_Pin_13;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
- /**************************************************************/
- /* For Remapped Ethernet pins */
- /*************************************************************/
- /* Input (Reset Value):
- - ETH_MII_CRS CRS: PA0
- - ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1
- - ETH_MII_COL: PA3
- - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8
- - ETH_MII_TX_CLK: PC3
- - ETH_MII_RXD0 / ETH_RMII_RXD0: PD9
- - ETH_MII_RXD1 / ETH_RMII_RXD1: PD10
- - ETH_MII_RXD2: PD11
- - ETH_MII_RXD3: PD12
- - ETH_MII_RX_ER: PB10 */
+ /**************************************************************/
+ /* For Remapped Ethernet pins */
+ /*************************************************************/
+ /* Input (Reset Value):
+ - ETH_MII_CRS CRS: PA0
+ - ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1
+ - ETH_MII_COL: PA3
+ - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8
+ - ETH_MII_TX_CLK: PC3
+ - ETH_MII_RXD0 / ETH_RMII_RXD0: PD9
+ - ETH_MII_RXD1 / ETH_RMII_RXD1: PD10
+ - ETH_MII_RXD2: PD11
+ - ETH_MII_RXD3: PD12
+ - ETH_MII_RX_ER: PB10 */
- /* Configure PA0, PA1 and PA3 as input */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
+ /* Configure PA0, PA1 and PA3 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
- /* Configure PB10 as input */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
+ /* Configure PB10 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
- /* Configure PC3 as input */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_Init(GPIOC, &GPIO_InitStructure);
+ /* Configure PC3 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
- /* Configure PD8, PD9, PD10, PD11 and PD12 as input */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_Init(GPIOD, &GPIO_InitStructure); /**/
+ /* Configure PD8, PD9, PD10, PD11 and PD12 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOD, &GPIO_InitStructure); /**/
- /* MCO pin configuration------------------------------------------------- */
- /* Configure MCO (PA8) as alternate function push-pull */
- //GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
- //GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- //GPIO_Init(GPIOA, &GPIO_InitStructure);
+ /* MCO pin configuration------------------------------------------------- */
+ /* Configure MCO (PA8) as alternate function push-pull */
+ //GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+ //GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ //GPIO_Init(GPIOA, &GPIO_InitStructure);
#endif
- return 0;
+ return 0;
}
int is_button_low(uint16_t GPIOpin)
{
- int result = 1;
+ int result = 1;
- if (GPIO_ReadInputDataBit(TA_BOOT1_GPIO, TA_BOOT1))
- result = 0;
+ if (GPIO_ReadInputDataBit(TA_BOOT1_GPIO, TA_BOOT1))
+ result = 0;
- return result;
+ return result;
}
//when switch (S1) is 'on' the pin is low
int is_switch_on(uint16_t GPIOpin)
{
- int result = 1;
+ int result = 1;
- if (GPIO_ReadInputDataBit(TA_SW1_GPIO, GPIOpin))
- result = 0;
+ if (GPIO_ReadInputDataBit(TA_SW1_GPIO, GPIOpin))
+ result = 0;
- return result;
+ return result;
}
void led_off (led_t led)
{
- switch (led)
- {
- case LED_PC6:
- GPIO_ResetBits(GPIOC, GPIO_Pin_6);
- break;
- case LED_PC7:
- GPIO_ResetBits(GPIOC, GPIO_Pin_7);
- break;
- case LED_PC8:
- GPIO_ResetBits(GPIOC, GPIO_Pin_8);
- break;
- case LED_PC9:
- GPIO_ResetBits(GPIOC, GPIO_Pin_9);
- break;
- case LED_ALL:
- GPIO_ResetBits(GPIOC, GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_6 | GPIO_Pin_7);
- break;
- default:
- // do nothing for undefined led number
- break;
- }
+ switch (led)
+ {
+ case LED_PC6:
+ GPIO_ResetBits(GPIOC, GPIO_Pin_6);
+ break;
+ case LED_PC7:
+ GPIO_ResetBits(GPIOC, GPIO_Pin_7);
+ break;
+ case LED_PC8:
+ GPIO_ResetBits(GPIOC, GPIO_Pin_8);
+ break;
+ case LED_PC9:
+ GPIO_ResetBits(GPIOC, GPIO_Pin_9);
+ break;
+ case LED_ALL:
+ GPIO_ResetBits(GPIOC, GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_6 | GPIO_Pin_7);
+ break;
+ default:
+ // do nothing for undefined led number
+ break;
+ }
}
void led_on (led_t led)
{
- switch (led)
- {
- case LED_PC6:
- GPIO_SetBits(GPIOC, GPIO_Pin_6);
- break;
- case LED_PC7:
- GPIO_SetBits(GPIOC, GPIO_Pin_7);
- break;
- case LED_PC8:
- GPIO_SetBits(GPIOC, GPIO_Pin_8);
- break;
- case LED_PC9:
- GPIO_SetBits(GPIOC, GPIO_Pin_9);
- break;
- case LED_ALL:
- GPIO_SetBits(GPIOC, GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_6 | GPIO_Pin_7);
- break;
- default:
- // do nothing for undefined led number
- break;
- }
+ switch (led)
+ {
+ case LED_PC6:
+ GPIO_SetBits(GPIOC, GPIO_Pin_6);
+ break;
+ case LED_PC7:
+ GPIO_SetBits(GPIOC, GPIO_Pin_7);
+ break;
+ case LED_PC8:
+ GPIO_SetBits(GPIOC, GPIO_Pin_8);
+ break;
+ case LED_PC9:
+ GPIO_SetBits(GPIOC, GPIO_Pin_9);
+ break;
+ case LED_ALL:
+ GPIO_SetBits(GPIOC, GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_6 | GPIO_Pin_7);
+ break;
+ default:
+ // do nothing for undefined led number
+ break;
+ }
}
#ifdef USART_SUPPORT
@@ -854,8 +856,8 @@
int is_IRQ_enabled(void)
{
- return (( NVIC->ISER[((uint32_t)(DECAIRQ_EXTI_IRQn) >> 5)]
- & (uint32_t)0x01 << (DECAIRQ_EXTI_IRQn & (uint8_t)0x1F) ) ? 1 : 0) ;
+ return (( NVIC->ISER[((uint32_t)(DECAIRQ_EXTI_IRQn) >> 5)]
+ & (uint32_t)0x01 << (DECAIRQ_EXTI_IRQn & (uint8_t)0x1F) ) ? 1 : 0) ;
}
/*! ------------------------------------------------------------------------------------------------------------------
@@ -913,9 +915,9 @@
*/
void peripherals_init (void)
{
- rcc_init();
- gpio_init();
- systick_init();
- spi_peripheral_init();
- usartinit();
+ rcc_init();
+ gpio_init();
+ systick_init();
+ spi_peripheral_init();
+ usartinit();
}
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.h"
index 7572a50..65d24cc 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/port.h"
@@ -27,9 +27,9 @@
#define CLOCKS_PER_SEC 1000
void printf2(const char *format, ...);
-
-void USART_puts(uint8_t *s,uint8_t len);
-
+
+void USART_puts(uint8_t *s, uint8_t len);
+
extern int writetospi_serial(uint16_t headerLength,
const uint8_t *headerBuffer,
uint32_t bodylength,
@@ -184,7 +184,7 @@
#define gpio_reset(x) 0
#define is_gpio_out_low(x) 0
#define is_gpio_out_high(x) 0
-
+
/*! ------------------------------------------------------------------------------------------------------------------
* @fn peripherals_init()
*
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/syscalls.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/syscalls.c"
index 510a501..d5576f4 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/syscalls.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/platform/syscalls.c"
@@ -36,11 +36,11 @@
prev_heap_end = heap_end;
- stack = (char*) port_GET_stack_pointer();
+ stack = (char *) port_GET_stack_pointer();
if (heap_end + incr > stack)
{
- return (caddr_t) -1;
+ return (caddr_t) - 1;
}
heap_end += incr;
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c"
index ddb1ab7..c86df78 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c"
@@ -1,11 +1,11 @@
/**
******************************************************************************
- * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
+ * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
* @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
+ * This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @copy
@@ -18,7 +18,7 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_it.h"
@@ -29,11 +29,11 @@
void SysTick_Handler(void)
{
time32_incr++;
- time32_reset++;
- if(time32_reset>10000)
- {
- NVIC_SystemReset();
- }
+ time32_reset++;
+ if(time32_reset > 10000)
+ {
+ NVIC_SystemReset();
+ }
}
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h"
index c7ac0b3..03a10a3 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h"
@@ -1,6 +1,6 @@
/**
******************************************************************************
- * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
+ * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
@@ -16,15 +16,15 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IT_H
#define __STM32F10x_IT_H
#ifdef __cplusplus
- extern "C" {
-#endif
+extern "C" {
+#endif
/*
* Tick timer interrupt handler to replace the default one.
--
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