From 8770b97111b845632246b08696f4362f6e88a5ee Mon Sep 17 00:00:00 2001
From: guanjiao <sqrgj@163.com>
Date: 星期六, 15 九月 2018 20:31:25 +0800
Subject: [PATCH] Merge branch 'dev_zyc' into Merge_anchor_and_tag
---
源码/核心板/Src/OnChipDevices/RTC.h | 10 ++
源码/核心板/Src/OnChipDevices/Spi.h | 2
源码/核心板/Src/application/dw_app.h | 1
源码/核心板/Src/main.c | 18 ++++
源码/核心板/Src/OnChipDevices/Rcc_Nvic_Systick.h | 2
.gitignore | 15 +++
源码/核心板/Src/stm32f10x_it.c | 14 +++
源码/核心板/Src/OnChipDevices/Rcc_Nvic_Systick.c | 7 +
源码/核心板/Src/stm32f10x_it.h | 2
源码/核心板/Src/OnChipDevices/RTC.c | 68 +++++++++++++++++
源码/核心板/Src/application/dw_app.c | 46 +++++++----
11 files changed, 164 insertions(+), 21 deletions(-)
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ed50861
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,15 @@
+
+*.txt
+*.crf
+*.d
+*.o
+*.ini
+*.dbgconf
+*.lst
+*.map
+*.iex
+*.dep
+*.axf
+*.htm
+*.lnp
+*.sct
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/RTC.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/RTC.c"
new file mode 100644
index 0000000..c952803
--- /dev/null
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/RTC.c"
@@ -0,0 +1,68 @@
+#include "RTC.h"
+
+
+void RTC_SET_ALARM(u32 sec)
+{
+ //DEBUG_COM_STREAM("-??-",NULL);
+ RTC_SetAlarm(RTC_GetCounter()+sec);
+ //DEBUG_COM_STREAM("-??1-",NULL);
+ RTC_WaitForLastTask();
+ //DEBUG_COM_STREAM("-??2-",NULL);
+ RTC_ITConfig(RTC_FLAG_ALR,ENABLE);
+}
+
+void RTC_Configuration(void)
+{
+ EXTI_InitTypeDef EXTI_InitStructure;
+
+ /* Enable PWR and BKP clocks */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
+
+ /* Allow access to BKP Domain */
+ PWR_BackupAccessCmd(ENABLE);
+
+ /* Reset Backup Domain */
+ //BKP_DeInit();
+
+ RCC_LSICmd(ENABLE);
+ /* Enable LSE */
+ //RCC_LSEConfig(RCC_LSE_ON);
+ /* Wait till LSE is ready */
+ while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET){}
+
+ /* Select LSE as RTC Clock Source */
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
+
+ /* Enable RTC Clock */
+ RCC_RTCCLKCmd(ENABLE);
+
+ /* Wait for RTC registers synchronization */
+ RTC_WaitForSynchro();
+
+ /* Wait until last write operation on RTC registers has finished */
+ RTC_WaitForLastTask();
+
+ /* Enable the RTC Second */
+ //RTC_ITConfig(RTC_IT_SEC, ENABLE);
+
+ /* Wait until last write operation on RTC registers has finished */
+ RTC_WaitForLastTask();
+
+ RTC_ITConfig(RTC_IT_ALR,ENABLE); //?? RTC ???
+ RTC_WaitForLastTask();
+ /* Set RTC prescaler: set RTC period to 1sec */
+ RTC_SetPrescaler(40000); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
+
+ /* Wait until last write operation on RTC registers has finished */
+ RTC_WaitForLastTask();
+ RTC_SET_ALARM(1);
+
+ //RTC外部中断使能
+ EXTI_InitStructure.EXTI_Line = EXTI_Line17;
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+ EXTI_Init(&EXTI_InitStructure);
+
+}
+
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/RTC.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/RTC.h"
new file mode 100644
index 0000000..0bcc693
--- /dev/null
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/RTC.h"
@@ -0,0 +1,10 @@
+#ifndef __RTC_H_
+#define __RTC_H_
+
+#include "stm32f10x.h"
+
+
+void RTC_Configuration(void);
+
+
+#endif
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.c"
index 38d4add..6e55e6b 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.c"
@@ -53,6 +53,13 @@
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+
+
+ NVIC_InitStructure.NVIC_IRQChannel = RTCAlarm_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd =ENABLE;
+
NVIC_Init(&NVIC_InitStructure);
}
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.h"
index 161a76f..fcd4f82 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Rcc_Nvic_Systick.h"
@@ -11,5 +11,5 @@
int Systick_Init(void);
void delay_us(uint32_t nTimer);
void delay_ms(uint32_t nTimer);
-
+void RTC_Configuration(void);
#endif
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Spi.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Spi.h"
index bdeaa69..f65cb8e 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Spi.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/OnChipDevices/Spi.h"
@@ -5,7 +5,7 @@
#include "stm32f10x.h"
#define SPIx_PRESCALER_SLOW SPI_BaudRatePrescaler_32
-#define SPIx_PRESCALER_FAST SPI_BaudRatePrescaler_8
+#define SPIx_PRESCALER_FAST SPI_BaudRatePrescaler_4
#define SPIx SPI1
#define SPIx_GPIO GPIOA
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.c"
index 64a0756..84ee3d2 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.c"
@@ -49,13 +49,13 @@
#define POLL_TX_TO_RESP_RX_DLY_UUS 150
/* This is the delay from Frame RX timestamp to TX reply timestamp used for calculating/setting the DW1000's delayed TX function. This includes the
* frame length of approximately 2.66 ms with above configuration. */
-#define RESP_RX_TO_FINAL_TX_DLY_UUS 4100
+#define RESP_RX_TO_FINAL_TX_DLY_UUS 1500
/* Receive response timeout. See NOTE 5 below. */
-#define RESP_RX_TIMEOUT_UUS 14700
+#define RESP_RX_TIMEOUT_UUS 2700
-#define POLL_RX_TO_RESP_TX_DLY_UUS 3600
+#define POLL_RX_TO_RESP_TX_DLY_UUS 420
/* This is the delay from the end of the frame transmission to the enable of the receiver, as programmed for the DW1000's wait for response feature. */
-#define RESP_TX_TO_FINAL_RX_DLY_UUS 500
+#define RESP_TX_TO_FINAL_RX_DLY_UUS 200
/* Receive final timeout. See NOTE 5 below. */
#define FINAL_RX_TIMEOUT_UUS 4300
@@ -78,18 +78,17 @@
/*------------------------------------ Variables ------------------------------------------*/
/* Default communication configuration. We use here EVK1000's default mode (mode 3). */
-static dwt_config_t config =
-{
- 2, /* Channel number. */
- DWT_PRF_64M, /* Pulse repetition frequency. */
- DWT_PLEN_1024, /* Preamble length. */
- DWT_PAC32, /* Preamble acquisition chunk size. Used in RX only. */
- 9, /* TX preamble code. Used in TX only. */
- 9, /* RX preamble code. Used in RX only. */
- 1, /* Use non-standard SFD (Boolean) */
- DWT_BR_110K, /* Data rate. */
- DWT_PHRMODE_STD, /* PHY header mode. */
- (1025 + 64 - 32) /* SFD timeout (preamble length + 1 + SFD length - PAC size). Used in RX only. */
+static dwt_config_t config = {
+ 5, /* Channel number. */
+ DWT_PRF_64M, /* Pulse repetition frequency. */
+ DWT_PLEN_128, /* Preamble length. */
+ DWT_PAC8, /* Preamble acquisition chunk size. Used in RX only. */
+ 9, /* TX preamble code. Used in TX only. */
+ 9, /* RX preamble code. Used in RX only. */
+ 0, /* Use non-standard SFD (Boolean) */
+ DWT_BR_6M8, /* Data rate. */
+ DWT_PHRMODE_STD, /* PHY header mode. */
+ (129 + 8 - 8) /* SFD timeout (preamble length + 1 + SFD length - PAC size). Used in RX only. */
};
/* Frames used in the ranging process. See NOTE 2 below. */
@@ -229,7 +228,9 @@
/* Configure DW1000. See NOTE 6 below. */
dwt_configure(&config);//配置DW1000
+
+
/* Apply default antenna delay value. See NOTE 1 below. */
dwt_setrxantennadelay(RX_ANT_DLY); //设置接收天线延迟
dwt_settxantennadelay(TX_ANT_DLY); //设置发射天线延迟
@@ -240,10 +241,20 @@
dwt_setrxtimeout(RESP_RX_TIMEOUT_UUS); //设置接收超时时间
}
+void tag_sleep_configuraion(void)
+{
+ dwt_configuresleep(0x940, 0x7);
+ dwt_entersleep();
+}
+
void Tag_App(void)//发送模式(TAG标签)
{
uint32_t frame_len;
uint32_t final_tx_time;
+
+ GPIO_ResetBits(SPIx_GPIO, SPIx_CS);
+ delay_us(2000);
+ GPIO_SetBits(SPIx_GPIO, SPIx_CS);
/* Write frame data to DW1000 and prepare transmission. See NOTE 7 below. */
tx_poll_msg[ALL_MSG_SN_IDX] = frame_seq_nb;
@@ -325,7 +336,8 @@
}
LED0_BLINK;
/* Execute a delay between ranging exchanges. */
- deca_sleep(RNG_DELAY_MS + random_delay_tim); //休眠固定时间
+ dwt_entersleep();
+
}
void Anchor_App(void)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.h"
index 3a2c837..3d77926 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/application/dw_app.h"
@@ -16,5 +16,6 @@
void Dw1000_Init(void);
void Tag_App(void);
void Anchor_App(void);
+void tag_sleep_configuraion(void);
#endif
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c"
index 8e7059e..c8760ae 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/main.c"
@@ -10,8 +10,8 @@
#include "serial_at_cmd_app.h"
#include "global_param.h"
-//#define WORK_MODE_TAG
-#define WORK_MODE_ANCHOR
+#define WORK_MODE_TAG
+//#define WORK_MODE_ANCHOR
void Device_Init(void)
{
@@ -19,6 +19,9 @@
SystemInit();
Nvic_Init();
Systick_Init();
+#ifdef WORK_MODE_TAG
+ RTC_Configuration();
+#endif
Led_Init();
Beep_Init();
DW_GPIO_Init();
@@ -44,6 +47,7 @@
*
* @return none
*/
+
int main(void)
{
@@ -51,11 +55,21 @@
Program_Init();
Dw1000_Init();
+#ifdef WORK_MODE_TAG
+ tag_sleep_configuraion();
+#endif
+
/* Loop forever initiating ranging exchanges. */
while(1)
{
#ifdef WORK_MODE_TAG
+ if(g_start_send_flag)
+ {
+ g_start_send_flag = 0;
Tag_App();
+ }
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+ PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
#else
Anchor_App();
#endif
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c"
index 620a1ca..c2822c2 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.c"
@@ -29,6 +29,8 @@
/* Tick timer count. */
volatile uint32_t time32_incr;
+uint8_t tt=0;
+uint8_t g_start_send_flag = 0;
void SysTick_Handler(void)
{
@@ -55,4 +57,16 @@
}
}
+void RTCAlarm_IRQHandler(void)
+{
+ EXTI_ClearITPendingBit(EXTI_Line17);
+ RTC_ClearITPendingBit(RTC_FLAG_ALR);
+ g_start_send_flag = 1;
+ RTC_SET_ALARM(1);
+ tt++;
+ //GPIO_Toggle(GPIOA,LED_PIN);
+
+ //SYS.wake_id|=1<<17;
+}
+
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h"
index 086c5d4..d9d1c78 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/stm32f10x_it.h"
@@ -27,6 +27,8 @@
#ifdef __cplusplus
extern "C" {
#endif
+
+extern uint8_t g_start_send_flag;
/*
* Tick timer interrupt handler to replace the default one.
--
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