From 12c64dd79ad5069e9e6ae50d7ee688edafe84f0f Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期四, 14 十一月 2019 17:41:29 +0800
Subject: [PATCH] 控制完成，纹波过大
---
源码/核心板/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"
index 71efc85..b6d3959 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"
@@ -1051,9 +1051,9 @@
RCC_CFGR_PLLMULL9);
#else
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE_HSE_Div2 |
RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_HSE_Div2|RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */
/* Enable PLL */
--
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