From a249d25e6f162ea7e17478010864193de4681b74 Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期三, 08 四月 2020 21:36:30 +0800
Subject: [PATCH] v1.20
---
源码/核心板/Src/decadriver/deca_device.c | 17 ++++++++++++++---
1 files changed, 14 insertions(+), 3 deletions(-)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
index fa05f24..8c7f1e0 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
@@ -153,9 +153,11 @@
#define VBAT_ADDRESS (0x08)
#define VTEMP_ADDRESS (0x09)
#define XTRIM_ADDRESS (0x1E)
-
+ u8 module_power;
int dwt_initialise(uint16_t config)
{
+
+ u32 power_temp,power_input;
uint8_t plllockdetect = EC_CTRL_PLLLCK;
uint16_t otp_addr = 0;
uint32_t ldo_tune = 0;
@@ -177,8 +179,17 @@
}
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
-
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+
+ if(module_power>36)
+ {
+ power_temp =(module_power-36);
+ }else{
+ power_temp = ((6-(module_power/6))<<5)|(module_power%6);
+ }
+ power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp;
+ dwt_write32bitreg(TX_POWER_ID, power_input);
+
+ //dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
// Configure the CPLL lock detect
dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
--
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