From a249d25e6f162ea7e17478010864193de4681b74 Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期三, 08 四月 2020 21:36:30 +0800
Subject: [PATCH] v1.20
---
源码/核心板/Src/decadriver/deca_device.c | 62 +++++++++++++++++++++++++++++-
1 files changed, 59 insertions(+), 3 deletions(-)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
index 75a99e4..8c7f1e0 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
@@ -103,15 +103,61 @@
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
// OTP addresses definitions
+#define CPUID_OTP_ADRESS 0x1d
+
+uint32_t ReadUniqueID(void)
+{
+ uint8_t m_UIDAdd[4];
+ uint32_t cpuID_add;
+ //获取CPU唯一ID
+// m_CpuID.Data32[0] = *(vu32*)(0x1ffff7e8);
+// m_CpuID.Data32[1] = *(vu32*)(0x1ffff7ec);
+// m_CpuID.Data32[2] = *(vu32*)(0x1ffff7f0);
+ //这里是防止反汇编能看到在哪里读取的UID，将UID的地址分解存在RAM中
+ //加密算法,很简单的加密算法
+ m_UIDAdd[0] = 0xE8;
+ m_UIDAdd[1] = m_UIDAdd[0]+0x0F; //f7 = e8 + 0f
+ m_UIDAdd[2] = m_UIDAdd[1]+0x08; //ff = f7 + 08
+ m_UIDAdd[3] = m_UIDAdd[2]-0xe0; //1f = ff - e0
+ memcpy(&cpuID_add, (uint8_t*)m_UIDAdd, 4);
+
+ return *(uint32_t*)(cpuID_add);
+}
+
+uint8_t UID_ERROR=0;
+void CheckCPUID(void)
+{ uint32_t cpuID = 0;
+ uint32_t key_ID = 0;
+ uint8_t i=10;
+ cpuID = ReadUniqueID();
+ Spi_ChangePrescaler(SPI_BaudRatePrescaler_256);
+ while(i--)
+ {
+ dwt_otpread(CPUID_OTP_ADRESS,&key_ID,1);
+ if(cpuID != key_ID)
+ {
+ UID_ERROR = 1;
+ }
+ else
+ {
+ UID_ERROR = 0;
+ break;
+ }
+}
+
+ Spi_ChangePrescaler(SPI_BaudRatePrescaler_8);
+}
#define LDOTUNE_ADDRESS (0x04)
#define PARTID_ADDRESS (0x06)
#define LOTID_ADDRESS (0x07)
#define VBAT_ADDRESS (0x08)
#define VTEMP_ADDRESS (0x09)
#define XTRIM_ADDRESS (0x1E)
-
+ u8 module_power;
int dwt_initialise(uint16_t config)
{
+
+ u32 power_temp,power_input;
uint8_t plllockdetect = EC_CTRL_PLLLCK;
uint16_t otp_addr = 0;
uint32_t ldo_tune = 0;
@@ -133,8 +179,17 @@
}
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
-
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+
+ if(module_power>36)
+ {
+ power_temp =(module_power-36);
+ }else{
+ power_temp = ((6-(module_power/6))<<5)|(module_power%6);
+ }
+ power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp;
+ dwt_write32bitreg(TX_POWER_ID, power_input);
+
+ //dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
// Configure the CPLL lock detect
dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
@@ -191,6 +246,7 @@
dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK);
}
+ CheckCPUID();
return DWT_SUCCESS ;
} // end dwt_initialise()
--
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