From a760912c22c9d85892313ae994ca9634dbe5f85d Mon Sep 17 00:00:00 2001
From: guanjiao <sqrgj@163.com>
Date: 星期一, 14 五月 2018 23:25:02 +0800
Subject: [PATCH] 分开各部分驱动
---
源码/核心板/Src/decadriver/deca_params_init.c | 59 ++++++++++++++++++++++++++++++-----------------------------
1 files changed, 30 insertions(+), 29 deletions(-)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c"
index e63772d..0e6603d 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_params_init.c"
@@ -27,12 +27,12 @@
//-----------------------------------------
const uint32 tx_config[NUM_CH] =
{
- RF_TXCTRL_CH1, /* Tx value match UM */
- RF_TXCTRL_CH2,
- RF_TXCTRL_CH3,
- RF_TXCTRL_CH4,
- RF_TXCTRL_CH5,
- RF_TXCTRL_CH7,
+ RF_TXCTRL_CH1, /* Tx value match UM */
+ RF_TXCTRL_CH2,
+ RF_TXCTRL_CH3,
+ RF_TXCTRL_CH4,
+ RF_TXCTRL_CH5,
+ RF_TXCTRL_CH7,
};
//RF -> Channel_Specific_Cfg -> Channel_Cfg -> RF_PLL -> RF PLL2
@@ -97,32 +97,33 @@
};
const uint32 digital_bb_config[NUM_PRF][NUM_PACS] =
+{
+ //16 PRF
{
- //16 PRF
- {
- //PAC 8
- 0x311A002D,
- //PAC 16
- 0x331A0052,
- //PAC 32
- 0x351A009A,
- //PAC 64
- 0x371A011D
- },
- //64 PRF
- {
- //PAC 8
- 0x313B006B,
- //PAC 16
- 0x333B00BE,
- //PAC 32
- 0x353B015E,
- //PAC 64
- 0x373B0296
- }
+ //PAC 8
+ 0x311A002D,
+ //PAC 16
+ 0x331A0052,
+ //PAC 32
+ 0x351A009A,
+ //PAC 64
+ 0x371A011D
+ },
+ //64 PRF
+ {
+ //PAC 8
+ 0x313B006B,
+ //PAC 16
+ 0x333B00BE,
+ //PAC 32
+ 0x353B015E,
+ //PAC 64
+ 0x373B0296
+ }
};
-const uint16 lde_replicaCoeff[PCODES] = {
+const uint16 lde_replicaCoeff[PCODES] =
+{
// 0
(int)(0.0 * 65536),
--
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