From b32e18a80201f1f285f172f07dda6b48beb6bab6 Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期六, 23 四月 2022 20:38:12 +0800
Subject: [PATCH] V2.49
---
源码/核心板/Src/decadriver/deca_device.c | 430 ++++++++++++++++++++++++++++-------------------------
1 files changed, 228 insertions(+), 202 deletions(-)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
index 407d576..9929e5e 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
@@ -10,7 +10,7 @@
*
*/
-#include "deca_types.h"
+#include <stddef.h>
#include "deca_param_types.h"
#include "deca_regs.h"
#include "deca_device_api.h"
@@ -41,9 +41,9 @@
// Load ucode from OTP/ROM
void _dwt_loaducodefromrom(void);
// Read non-volatile memory
-uint32 _dwt_otpread(uint32 address);
+uint32_t _dwt_otpread(uint32_t address);
// Program the non-volatile memory
-uint32 _dwt_otpprogword32(uint32 data, uint16 address);
+uint32_t _dwt_otpprogword32(uint32_t data, uint16_t address);
// Upload the device configuration into always on memory
void _dwt_aonarrayupload(void);
// -------------------------------------------------------------------------------------------------------------------
@@ -56,21 +56,21 @@
// Structure to hold device data
typedef struct
{
- uint32 deviceID ;
- uint32 partID ;
- uint32 lotID ;
- uint8 chan; // Added channel here - used in the reading of accumulator
- uint8 longFrames ; // Flag in non-standard long frame mode
- uint8 otprev ; // OTP revision number (read during initialisation)
- uint32 txFCTRL ; // Keep TX_FCTRL register config
- uint8 xtrim; // XTAL trim value read from OTP
- uint8 dblbuffon; // Double RX buffer mode flag
- uint32 sysCFGreg ; // Local copy of system config register
- uint16 sleep_mode; // Used for automatic reloading of LDO tune and microcode at wake-up
+ uint32_t deviceID ;
+ uint32_t partID ;
+ uint32_t lotID ;
+ uint8_t chan; // Added channel here - used in the reading of accumulator
+ uint8_t longFrames ; // Flag in non-standard long frame mode
+ uint8_t otprev ; // OTP revision number (read during initialisation)
+ uint32_t txFCTRL ; // Keep TX_FCTRL register config
+ uint8_t xtrim; // XTAL trim value read from OTP
+ uint8_t dblbuffon; // Double RX buffer mode flag
+ uint32_t sysCFGreg ; // Local copy of system config register
+ uint16_t sleep_mode; // Used for automatic reloading of LDO tune and microcode at wake-up
dwt_callback_data_t cdata; // Callback data structure
- uint8 wait4resp ; // wait4response was set with last TX start command
+ uint8_t wait4resp ; // wait4response was set with last TX start command
int prfIndex ;
void (*dwt_txcallback)(const dwt_callback_data_t *txd);
@@ -109,12 +109,15 @@
#define VBAT_ADDRESS (0x08)
#define VTEMP_ADDRESS (0x09)
#define XTRIM_ADDRESS (0x1E)
-
-int dwt_initialise(uint16 config)
+u8 module_power;
+uint32_t status_reg = 0;
+int dwt_initialise(uint16_t config)
{
- uint8 plllockdetect = EC_CTRL_PLLLCK;
- uint16 otp_addr = 0;
- uint32 ldo_tune = 0;
+
+ u32 power_temp,power_input;
+ uint8_t plllockdetect = EC_CTRL_PLLLCK;
+ uint16_t otp_addr = 0;
+ uint32_t ldo_tune = 0;
dw1000local.dblbuffon = 0; // Double buffer mode off by default
dw1000local.prfIndex = 0; // 16MHz
@@ -124,29 +127,41 @@
dw1000local.dwt_txcallback = NULL ;
dw1000local.dwt_rxcallback = NULL ;
-
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
+ status_reg = dwt_read32bitreg(SYS_STATUS_ID);
// Read and validate device ID return -1 if not recognised
dw1000local.deviceID = dwt_readdevid() ;
- if (DWT_DEVICE_ID != dw1000local.deviceID) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
+ while (DWT_DEVICE_ID != dw1000local.deviceID) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
{
- return DWT_ERROR ;
+ dw1000local.deviceID = dwt_readdevid() ;
}
-
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
-
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+ status_reg = dwt_read32bitreg(SYS_STATUS_ID);
+ if(module_power>67)
+ {module_power=67;}
+ if(module_power<0)
+ {module_power=0;}
+ if(module_power>36)
+ {
+ power_temp =(module_power-36);
+ }else{
+ power_temp = ((6-(module_power/6))<<5)|(module_power%6);
+ }
+ power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp;
+ dwt_write32bitreg(TX_POWER_ID, power_input);
// Configure the CPLL lock detect
dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
// Read OTP revision number
otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte
-
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
// Load LDO tune from OTP and kick it if there is a value actually programmed.
ldo_tune = _dwt_otpread(LDOTUNE_ADDRESS);
if((ldo_tune & 0xFF) != 0)
{
- uint8 ldok = OTP_SF_LDO_KICK;
+ uint8_t ldok = OTP_SF_LDO_KICK;
// Kick LDO tune
dwt_writetodevice(OTP_IF_ID, OTP_SF, 1, &ldok); // Set load LDE kick bit
dw1000local.sleep_mode |= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
@@ -155,7 +170,7 @@
// Load Part and Lot ID from OTP
dw1000local.partID = _dwt_otpread(PARTID_ADDRESS);
dw1000local.lotID = _dwt_otpread(LOTID_ADDRESS);
-
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
// XTAL trim value is set in OTP for DW1000 module and EVK/TREK boards but that might not be the case in a custom design
dw1000local.xtrim = otp_addr & 0x1F;
if (!dw1000local.xtrim) // A value of 0 means that the crystal has not been trimmed
@@ -165,6 +180,8 @@
// Configure XTAL trim
dwt_xtaltrim(dw1000local.xtrim);
+ status_reg = dwt_read32bitreg(SYS_STATUS_ID);
+
// Load leading edge detect code
if(config & DWT_LOADUCODE)
{
@@ -173,7 +190,7 @@
}
else // Should disable the LDERUN enable bit in 0x36, 0x4
{
- uint16 rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET + 1) ;
+ uint16_t rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET + 1) ;
rega &= 0xFDFF ; // Clear LDERUN bit
dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET + 1, rega) ;
}
@@ -182,7 +199,16 @@
// Read system register / store local copy
dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
-
+ {
+ uint32_t reg;
+ reg = dwt_read32bitreg(GPIO_CTRL_ID);
+ reg |= 0x00014000;
+ reg |= 0x00050000;
+ dwt_write32bitreg(GPIO_CTRL_ID,reg);
+ dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK);
+
+ }
+ dw1000local.deviceID = dwt_readdevid() ;
return DWT_SUCCESS ;
} // end dwt_initialise()
@@ -198,7 +224,7 @@
*
* returns the read OTP revision value
*/
-uint8 dwt_otprevision(void)
+uint8_t dwt_otprevision(void)
{
return dw1000local.otprev ;
}
@@ -216,7 +242,7 @@
*/
void dwt_setGPIOforEXTTRX(void)
{
- uint8 buf[GPIO_MODE_LEN];
+ uint8_t buf[GPIO_MODE_LEN];
// Set the GPIO to control external PA/LNA
dwt_readfromdevice(GPIO_CTRL_ID, GPIO_MODE_OFFSET, GPIO_MODE_LEN, buf);
@@ -240,10 +266,10 @@
*
* no return value
*/
-void dwt_setGPIOdirection(uint32 gpioNum, uint32 direction)
+void dwt_setGPIOdirection(uint32_t gpioNum, uint32_t direction)
{
- uint8 buf[GPIO_DIR_LEN];
- uint32 command = direction | gpioNum;
+ uint8_t buf[GPIO_DIR_LEN];
+ uint32_t command = direction | gpioNum;
buf[0] = command & 0xff;
buf[1] = (command >> 8) & 0xff;
@@ -265,10 +291,10 @@
*
* no return value
*/
-void dwt_setGPIOvalue(uint32 gpioNum, uint32 value)
+void dwt_setGPIOvalue(uint32_t gpioNum, uint32_t value)
{
- uint8 buf[GPIO_DOUT_LEN];
- uint32 command = value | gpioNum;
+ uint8_t buf[GPIO_DOUT_LEN];
+ uint32_t command = value | gpioNum;
buf[0] = command & 0xff;
buf[1] = (command >> 8) & 0xff;
@@ -288,7 +314,7 @@
*
* returns the 32 bit part ID value as programmed in the factory
*/
-uint32 dwt_getpartid(void)
+uint32_t dwt_getpartid(void)
{
return dw1000local.partID;
}
@@ -304,7 +330,7 @@
*
* returns the 32 bit lot ID value as programmed in the factory
*/
-uint32 dwt_getlotid(void)
+uint32_t dwt_getlotid(void)
{
return dw1000local.lotID;
}
@@ -320,7 +346,7 @@
*
* returns the read value which for DW1000 is 0xDECA0130
*/
-uint32 dwt_readdevid(void)
+uint32_t dwt_readdevid(void)
{
return dwt_read32bitoffsetreg(DEV_ID_ID, 0);
}
@@ -367,13 +393,13 @@
*/
int dwt_configure(dwt_config_t *config)
{
- uint8 nsSfd_result = 0;
- uint8 useDWnsSFD = 0;
- uint8 chan = config->chan ;
- uint32 regval ;
- uint16 reg16 = lde_replicaCoeff[config->rxCode];
- uint8 prfIndex = dw1000local.prfIndex = config->prf - DWT_PRF_16M;
- uint8 bw = ((chan == 4) || (chan == 7)) ? 1 : 0 ; // Select wide or narrow band
+ uint8_t nsSfd_result = 0;
+ uint8_t useDWnsSFD = 0;
+ uint8_t chan = config->chan ;
+ uint32_t regval ;
+ uint16_t reg16 = lde_replicaCoeff[config->rxCode];
+ uint8_t prfIndex = dw1000local.prfIndex = config->prf - DWT_PRF_16M;
+ uint8_t bw = ((chan == 4) || (chan == 7)) ? 1 : 0 ; // Select wide or narrow band
dw1000local.chan = config->chan ;
@@ -473,13 +499,13 @@
{
if(config->txPreambLength == DWT_PLEN_64)
{
- uint8 temp = 0x10;
+ uint8_t temp = 0x10;
dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, 0x10);
dwt_writetodevice(DRX_CONF_ID, 0x26, 1, &temp);
}
else
{
- uint8 temp = 0x28;
+ uint8_t temp = 0x28;
dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, 0x20);
dwt_writetodevice(DRX_CONF_ID, 0x26, 1, &temp);
}
@@ -541,7 +567,7 @@
*
* no return value
*/
-void dwt_setrxantennadelay(uint16 rxDelay)
+void dwt_setrxantennadelay(uint16_t rxDelay)
{
// Set the RX antenna delay for auto TX timestamp adjustment
dwt_write16bitoffsetreg(LDE_IF_ID, LDE_RXANTD_OFFSET, rxDelay);
@@ -560,7 +586,7 @@
*
* no return value
*/
-void dwt_settxantennadelay(uint16 txDelay)
+void dwt_settxantennadelay(uint16_t txDelay)
{
// Set the TX antenna delay for auto TX timestamp adjustment
dwt_write16bitoffsetreg(TX_ANTD_ID, 0x0, txDelay);
@@ -586,7 +612,7 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_writetxdata(uint16 txFrameLength, uint8 *txFrameBytes, uint16 txBufferOffset)
+int dwt_writetxdata(uint16_t txFrameLength, uint8_t *txFrameBytes, uint16_t txBufferOffset)
{
#ifdef DWT_API_ERROR_CHECK
if (dw1000local.longFrames)
@@ -636,7 +662,7 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_writetxfctrl(uint16 txFrameLength, uint16 txBufferOffset)
+int dwt_writetxfctrl(uint16_t txFrameLength, uint16_t txBufferOffset)
{
#ifdef DWT_API_ERROR_CHECK
@@ -662,7 +688,7 @@
// Write the frame length to the TX frame control register
// dw1000local.txFCTRL has kept configured bit rate information
- uint32 reg32 = dw1000local.txFCTRL | txFrameLength | (txBufferOffset << 22);
+ uint32_t reg32 = dw1000local.txFCTRL | txFrameLength | (txBufferOffset << 22);
dwt_write32bitoffsetreg(TX_FCTRL_ID, 0, reg32) ;
return DWT_SUCCESS ;
@@ -684,7 +710,7 @@
*
* no return value
*/
-void dwt_readrxdata(uint8 *buffer, uint16 length, uint16 rxBufferOffset)
+void dwt_readrxdata(uint8_t *buffer, uint16_t length, uint16_t rxBufferOffset)
{
dwt_readfromdevice(RX_BUFFER_ID, rxBufferOffset, length, buffer) ;
}
@@ -703,7 +729,7 @@
*
* no return value
*/
-void dwt_readaccdata(uint8 *buffer, uint16 len, uint16 accOffset)
+void dwt_readaccdata(uint8_t *buffer, uint16_t len, uint16_t accOffset)
{
// Force on the ACC clocks if we are sequenced
_dwt_enableclocks(READ_ACC_ON);
@@ -734,7 +760,7 @@
diagnostics->maxNoise = dwt_read16bitoffsetreg(LDE_IF_ID, LDE_THRESH_OFFSET);
// Read all 8 bytes in one SPI transaction
- dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8 *)&diagnostics->stdNoise);
+ dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8_t *)&diagnostics->stdNoise);
//diagnostics->stdNoise = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x0) ;
//diagnostics->firstPathAmp2 = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x2) ;
//diagnostics->firstPathAmp3 = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x4) ;
@@ -761,7 +787,7 @@
*
* no return value
*/
-void dwt_readtxtimestamp(uint8 *timestamp)
+void dwt_readtxtimestamp(uint8_t *timestamp)
{
dwt_readfromdevice(TX_TIME_ID, 0, TX_TIME_TX_STAMP_LEN, timestamp) ; // Read bytes directly into buffer
}
@@ -777,7 +803,7 @@
*
* returns high 32-bits of TX timestamp
*/
-uint32 dwt_readtxtimestamphi32(void)
+uint32_t dwt_readtxtimestamphi32(void)
{
return dwt_read32bitoffsetreg(TX_TIME_ID, 1);
}
@@ -793,7 +819,7 @@
*
* returns low 32-bits of TX timestamp
*/
-uint32 dwt_readtxtimestamplo32(void)
+uint32_t dwt_readtxtimestamplo32(void)
{
return dwt_read32bitoffsetreg(TX_TIME_ID, 0);
}
@@ -810,7 +836,7 @@
*
* no return value
*/
-void dwt_readrxtimestamp(uint8 *timestamp)
+void dwt_readrxtimestamp(uint8_t *timestamp)
{
dwt_readfromdevice(RX_TIME_ID, 0, RX_TIME_RX_STAMP_LEN, timestamp) ; // Get the adjusted time of arrival
}
@@ -826,7 +852,7 @@
*
* returns high 32-bits of RX timestamp
*/
-uint32 dwt_readrxtimestamphi32(void)
+uint32_t dwt_readrxtimestamphi32(void)
{
return dwt_read32bitoffsetreg(RX_TIME_ID, 1);
}
@@ -842,7 +868,7 @@
*
* returns low 32-bits of RX timestamp
*/
-uint32 dwt_readrxtimestamplo32(void)
+uint32_t dwt_readrxtimestamplo32(void)
{
return dwt_read32bitoffsetreg(RX_TIME_ID, 0);
}
@@ -858,7 +884,7 @@
*
* returns high 32-bits of system time timestamp
*/
-uint32 dwt_readsystimestamphi32(void)
+uint32_t dwt_readsystimestamphi32(void)
{
return dwt_read32bitoffsetreg(SYS_TIME_ID, 1);
}
@@ -876,7 +902,7 @@
*
* no return value
*/
-void dwt_readsystime(uint8 *timestamp)
+void dwt_readsystime(uint8_t *timestamp)
{
dwt_readfromdevice(SYS_TIME_ID, 0, SYS_TIME_LEN, timestamp) ;
}
@@ -907,13 +933,13 @@
*/
int dwt_writetodevice
(
- uint16 recordNumber,
- uint16 index,
- uint32 length,
- const uint8 *buffer
+ uint16_t recordNumber,
+ uint16_t index,
+ uint32_t length,
+ const uint8_t *buffer
)
{
- uint8 header[3] ; // Buffer to compose header in
+ uint8_t header[3] ; // Buffer to compose header in
int cnt = 0; // Counter for length of header
#ifdef DWT_API_ERROR_CHECK
if (recordNumber > 0x3F)
@@ -943,12 +969,12 @@
if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
{
- header[cnt++] = (uint8)index ; // Bit-7 zero means no extension, bits 6-0 is index.
+ header[cnt++] = (uint8_t)index ; // Bit-7 zero means no extension, bits 6-0 is index.
}
else
{
- header[cnt++] = 0x80 | (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
- header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
+ header[cnt++] = 0x80 | (uint8_t)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
+ header[cnt++] = (uint8_t) (index >> 7) ; // 8-bit value = high eight bits of index.
}
}
@@ -982,13 +1008,13 @@
*/
int dwt_readfromdevice
(
- uint16 recordNumber,
- uint16 index,
- uint32 length,
- uint8 *buffer
+ uint16_t recordNumber,
+ uint16_t index,
+ uint32_t length,
+ uint8_t *buffer
)
{
- uint8 header[3] ; // Buffer to compose header in
+ uint8_t header[3] ; // Buffer to compose header in
int cnt = 0; // Counter for length of header
#ifdef DWT_API_ERROR_CHECK
if (recordNumber > 0x3F)
@@ -1000,7 +1026,7 @@
// Write message header selecting READ operation and addresses as appropriate (this is one to three bytes long)
if (index == 0) // For index of 0, no sub-index is required
{
- header[cnt++] = (uint8) recordNumber ; // Bit-7 zero is READ operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
+ header[cnt++] = (uint8_t) recordNumber ; // Bit-7 zero is READ operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
}
else
{
@@ -1014,16 +1040,16 @@
return DWT_ERROR ; // Sub-addressable area is limited to 15-bits.
}
#endif
- header[cnt++] = (uint8)(0x40 | recordNumber) ; // Bit-7 zero is READ operation, bit-6 one=sub-address follows, bits 5-0 is reg file id
+ header[cnt++] = (uint8_t)(0x40 | recordNumber) ; // Bit-7 zero is READ operation, bit-6 one=sub-address follows, bits 5-0 is reg file id
if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
{
- header[cnt++] = (uint8) index ; // Bit-7 zero means no extension, bits 6-0 is index.
+ header[cnt++] = (uint8_t) index ; // Bit-7 zero means no extension, bits 6-0 is index.
}
else
{
- header[cnt++] = 0x80 | (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
- header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
+ header[cnt++] = 0x80 | (uint8_t)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
+ header[cnt++] = (uint8_t) (index >> 7) ; // 8-bit value = high eight bits of index.
}
}
@@ -1047,11 +1073,11 @@
*
* returns 32 bit register value (success), or DWT_ERROR for error
*/
-uint32 dwt_read32bitoffsetreg(int regFileID, int regOffset)
+uint32_t dwt_read32bitoffsetreg(int regFileID, int regOffset)
{
- uint32 regval = (uint32)DWT_ERROR ;
+ uint32_t regval = (uint32_t)DWT_ERROR ;
int j ;
- uint8 buffer[4] ;
+ uint8_t buffer[4] ;
int result = dwt_readfromdevice(regFileID, regOffset, 4, buffer); // Read 4 bytes (32-bits) register into buffer
@@ -1079,10 +1105,10 @@
*
* returns 16 bit register value (success), or DWT_ERROR for error
*/
-uint16 dwt_read16bitoffsetreg(int regFileID, int regOffset)
+uint16_t dwt_read16bitoffsetreg(int regFileID, int regOffset)
{
- uint16 regval = (uint16)DWT_ERROR ;
- uint8 buffer[2] ;
+ uint16_t regval = (uint16_t)DWT_ERROR ;
+ uint8_t buffer[2] ;
int result = dwt_readfromdevice(regFileID, regOffset, 2, buffer); // Read 2 bytes (16-bits) register into buffer
@@ -1108,10 +1134,10 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_write16bitoffsetreg(int regFileID, int regOffset, uint16 regval)
+int dwt_write16bitoffsetreg(int regFileID, int regOffset, uint16_t regval)
{
int reg;
- uint8 buffer[2] ;
+ uint8_t buffer[2] ;
buffer[0] = regval & 0xFF;
buffer[1] = regval >> 8 ;
@@ -1136,11 +1162,11 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_write32bitoffsetreg(int regFileID, int regOffset, uint32 regval)
+int dwt_write32bitoffsetreg(int regFileID, int regOffset, uint32_t regval)
{
int j ;
int reg;
- uint8 buffer[4] ;
+ uint8_t buffer[4] ;
for ( j = 0 ; j < 4 ; j++ )
{
@@ -1174,9 +1200,9 @@
*
* no return value
*/
-void dwt_enableframefilter(uint16 enable)
+void dwt_enableframefilter(uint16_t enable)
{
- uint32 sysconfig = SYS_CFG_MASK & dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
+ uint32_t sysconfig = SYS_CFG_MASK & dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
if(enable)
{
@@ -1205,7 +1231,7 @@
*
* no return value
*/
-void dwt_setpanid(uint16 panID)
+void dwt_setpanid(uint16_t panID)
{
// PAN ID is high 16 bits of register
dwt_write16bitoffsetreg(PANADR_ID, 2, panID) ;
@@ -1223,7 +1249,7 @@
*
* no return value
*/
-void dwt_setaddress16(uint16 shortAddress)
+void dwt_setaddress16(uint16_t shortAddress)
{
// Short address into low 16 bits
dwt_write16bitoffsetreg(PANADR_ID, 0, shortAddress) ;
@@ -1241,7 +1267,7 @@
*
* no return value
*/
-void dwt_seteui(uint8 *eui64)
+void dwt_seteui(uint8_t *eui64)
{
dwt_writetodevice(EUI_64_ID, 0x0, 8, eui64);
}
@@ -1258,7 +1284,7 @@
*
* no return value
*/
-void dwt_geteui(uint8 *eui64)
+void dwt_geteui(uint8_t *eui64)
{
dwt_readfromdevice(EUI_64_ID, 0x0, 8, eui64);
}
@@ -1277,7 +1303,7 @@
*
* no return value
*/
-void dwt_otpread(uint32 address, uint32 *array, uint8 length)
+void dwt_otpread(uint32_t address, uint32_t *array, uint8_t length)
{
int i;
@@ -1305,10 +1331,10 @@
*
* returns the 32bit of read data
*/
-uint32 _dwt_otpread(uint32 address)
+uint32_t _dwt_otpread(uint32_t address)
{
- uint8 buf[4];
- uint32 ret_data;
+ uint8_t buf[4];
+ uint32_t ret_data;
buf[1] = (address >> 8) & 0xff;
buf[0] = address & 0xff;
@@ -1349,11 +1375,11 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-uint32 _dwt_otpsetmrregs(int mode)
+uint32_t _dwt_otpsetmrregs(int mode)
{
- uint8 rd_buf[4];
- uint8 wr_buf[4];
- uint32 mra = 0, mrb = 0, mr = 0;
+ uint8_t rd_buf[4];
+ uint8_t wr_buf[4];
+ uint32_t mra = 0, mrb = 0, mr = 0;
//printf("OTP SET MR: Setting MR,MRa,MRb for mode %2x\n",mode);
// PROGRAMME MRA
@@ -1396,7 +1422,7 @@
break;
default :
// printf("OTP SET MR: ERROR : Invalid mode selected\n",mode);
- return (uint32)DWT_ERROR;
+ return (uint32_t)DWT_ERROR;
}
wr_buf[0] = mra & 0x00ff;
@@ -1518,11 +1544,11 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-uint32 _dwt_otpprogword32(uint32 data, uint16 address)
+uint32_t _dwt_otpprogword32(uint32_t data, uint16_t address)
{
- uint8 rd_buf[1];
- uint8 wr_buf[4];
- uint8 otp_done;
+ uint8_t rd_buf[1];
+ uint8_t wr_buf[4];
+ uint8_t otp_done;
// Read status register
dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
@@ -1530,7 +1556,7 @@
if((rd_buf[0] & 0x02) != 0x02)
{
// printf("OTP PROG 32: ERROR VPP NOT OK, programming will fail. Are MR/MRA/MRB set?\n");
- return (uint32)DWT_ERROR;
+ return (uint32_t)DWT_ERROR;
}
// Write the data
@@ -1580,7 +1606,7 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-uint32 dwt_otpwriteandverify(uint32 value, uint16 address)
+uint32_t dwt_otpwriteandverify(uint32_t value, uint16_t address)
{
int prog_ok = DWT_SUCCESS;
int retry = 0;
@@ -1637,7 +1663,7 @@
*/
void _dwt_aonconfigupload(void)
{
- uint8 buf[1];
+ uint8_t buf[1];
buf[0] = 0x04;
dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
@@ -1659,7 +1685,7 @@
*/
void _dwt_aonarrayupload(void)
{
- uint8 buf[1];
+ uint8_t buf[1];
buf[0] = 0x00;
dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
@@ -1699,9 +1725,9 @@
*
* no return value
*/
-void dwt_configuresleepcnt(uint16 sleepcnt)
+void dwt_configuresleepcnt(uint16_t sleepcnt)
{
- uint8 buf[2];
+ uint8_t buf[2];
buf[0] = 0x01;
dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);
@@ -1743,10 +1769,10 @@
*
* returns the number of XTAL/2 cycles per low-power oscillator cycle. LP OSC frequency = 19.2 MHz/return value
*/
-uint16 dwt_calibratesleepcnt(void)
+uint16_t dwt_calibratesleepcnt(void)
{
- uint8 buf[2];
- uint16 result;
+ uint8_t buf[2];
+ uint16_t result;
// Enable cal of the sleep counter
buf[0] = 4;
@@ -1840,9 +1866,9 @@
*
* no return value
*/
-void dwt_configuresleep(uint16 mode, uint8 wake)
+void dwt_configuresleep(uint16_t mode, uint8_t wake)
{
- uint8 buf[1];
+ uint8_t buf[1];
// Add predefined sleep settings before writing the mode
mode |= dw1000local.sleep_mode;
@@ -1871,7 +1897,7 @@
*/
void dwt_entersleepaftertx(int enable)
{
- uint32 reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
+ uint32_t reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
// Set the auto TX -> sleep bit
if(enable)
{
@@ -1908,7 +1934,7 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_spicswakeup(uint8 *buff, uint16 length)
+int dwt_spicswakeup(uint8_t *buff, uint16_t length)
{
if(dwt_readdevid() != DWT_DEVICE_ID) // Device was in deep sleep (the first read fails)
{
@@ -1946,17 +1972,17 @@
*/
void _dwt_configlde(int prfIndex)
{
- uint8 x = LDE_PARAM1;
+ uint8_t x = LDE_PARAM1;
dwt_writetodevice( LDE_IF_ID, LDE_CFG1_OFFSET, 1, &x ); // 8-bit configuration register
if(prfIndex)
{
- dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_64); // 16-bit LDE configuration tuning register
+ dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16_t) LDE_PARAM3_64); // 16-bit LDE configuration tuning register
}
else
{
- dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_16);
+ dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16_t) LDE_PARAM3_16);
}
}
@@ -1974,7 +2000,7 @@
*/
void _dwt_loaducodefromrom(void)
{
- uint8 wr_buf[2];
+ uint8_t wr_buf[2];
// Set up clocks
wr_buf[1] = 0x03;
@@ -2004,10 +2030,10 @@
*
* no return value
*/
-void dwt_loadopsettabfromotp(uint8 gtab_sel)
+void dwt_loadopsettabfromotp(uint8_t gtab_sel)
{
- uint8 wr_buf[2];
- uint16 reg = (((gtab_sel & 0x3) << 5) | 0x1);
+ uint8_t wr_buf[2];
+ uint16_t reg = (((gtab_sel & 0x3) << 5) | 0x1);
// Set up clocks
wr_buf[1] = 0x03;
wr_buf[0] = 0x01;
@@ -2065,7 +2091,7 @@
*
* no return value
*/
-void dwt_enableautoack(uint8 responseDelayTime)
+void dwt_enableautoack(uint8_t responseDelayTime)
{
// Set auto ACK reply delay
dwt_write16bitoffsetreg(ACK_RESP_T_ID, 0x2, (responseDelayTime << 8) ) ; //in symbols
@@ -2118,7 +2144,7 @@
*/
void dwt_setautorxreenable(int enable)
{
- uint8 byte = 0;
+ uint8_t byte = 0;
if(enable)
{
@@ -2148,9 +2174,9 @@
*
* no return value
*/
-void dwt_setrxaftertxdelay(uint32 rxDelayTime)
+void dwt_setrxaftertxdelay(uint32_t rxDelayTime)
{
- uint32 val = dwt_read32bitreg(ACK_RESP_T_ID) ; // Read ACK_RESP_T_ID register
+ uint32_t val = dwt_read32bitreg(ACK_RESP_T_ID) ; // Read ACK_RESP_T_ID register
val &= ~(ACK_RESP_T_W4R_TIM_MASK) ; // Clear the timer (19:0)
@@ -2190,9 +2216,9 @@
*
* return value is 1 if the IRQS bit is set and 0 otherwise
*/
-uint8 dwt_checkIRQ(void)
+uint8_t dwt_checkIRQ(void)
{
- uint8 temp;
+ uint8_t temp;
dwt_readfromdevice(SYS_STATUS_ID, 0, 1, &temp);
@@ -2217,8 +2243,8 @@
*/
void dwt_isr(void) // Assume interrupt can supply context
{
- uint32 status = 0;
- uint32 clear = 0; // Will clear any events seen
+ uint32_t status = 0;
+ uint32_t clear = 0; // Will clear any events seen
dw1000local.cdata.event = 0;
dw1000local.cdata.dblbuff = dw1000local.dblbuffon ;
@@ -2254,7 +2280,7 @@
// Re-enable the receiver - if auto RX re-enable set
if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR)
{
- dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
}
else
{
@@ -2278,7 +2304,7 @@
// Read frame info and other registers and check for overflow again
// If overflow set then discard both frames...
- uint16 len = 0;
+ uint16_t len = 0;
if (status & SYS_STATUS_RXOVRR) // NOTE when overrun both HS and RS pointers point to the same buffer
{
@@ -2291,7 +2317,7 @@
if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here (ignore error)
{
- dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
}
else // The RX will be re-enabled by the application, report an error
{
@@ -2350,8 +2376,8 @@
}
else // Double buffer
{
- uint8 buff ;
- uint8 hsrb = 0x01 ;
+ uint8_t buff ;
+ uint8_t hsrb = 0x01 ;
// Need to make sure that the host/IC buffer pointers are aligned before starting RX
// Read again because the status could have changed since the interrupt was triggered
@@ -2368,7 +2394,7 @@
if((dw1000local.sysCFGreg & SYS_CFG_RXAUTR) == 0) // Double buffer is on but no auto RX re-enable RX
{
- dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
}
// Call the RX call-back function to process the RX event
@@ -2393,7 +2419,7 @@
if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here
{
- dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16)SYS_CTRL_RXENAB) ;
+ dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
}
}
} // end of else double buffer
@@ -2526,9 +2552,9 @@
*
* no return value
*/
-void dwt_setleds(uint8 test)
+void dwt_setleds(uint8_t test)
{
- uint8 buf[2];
+ uint8_t buf[2];
if(test & 0x1)
{
@@ -2582,7 +2608,7 @@
*/
void _dwt_enableclocks(int clocks)
{
- uint8 reg[2];
+ uint8_t reg[2];
dwt_readfromdevice(PMSC_ID, PMSC_CTRL0_OFFSET, 2, reg);
switch(clocks)
@@ -2675,7 +2701,7 @@
*
* no return value
*/
-void dwt_setdelayedtrxtime(uint32 starttime)
+void dwt_setdelayedtrxtime(uint32_t starttime)
{
dwt_write32bitoffsetreg(DX_TIME_ID, 1, starttime) ;
@@ -2696,25 +2722,25 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error (e.g. a delayed transmission will fail if the delayed time has passed)
*/
-int dwt_starttx(uint8 mode)
+int dwt_starttx(uint8_t mode)
{
int retval = DWT_SUCCESS ;
- uint8 temp = 0x00;
- uint16 checkTxOK = 0 ;
+ uint8_t temp = 0x00;
+ uint16_t checkTxOK = 0 ;
if(mode & DWT_RESPONSE_EXPECTED)
{
- temp = (uint8)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
+ temp = (uint8_t)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
dw1000local.wait4resp = 1;
}
if (mode & DWT_START_TX_DELAYED)
{
- //uint32 status ;
+ //uint32_t status ;
// Both SYS_CTRL_TXSTRT and SYS_CTRL_TXDLYS to correctly enable TX
- temp |= (uint8)(SYS_CTRL_TXDLYS | SYS_CTRL_TXSTRT) ;
+ temp |= (uint8_t)(SYS_CTRL_TXDLYS | SYS_CTRL_TXSTRT) ;
dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID, 3) ;
//status = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register
@@ -2727,7 +2753,7 @@
{
// I am taking DSHP set to Indicate that the TXDLYS was set too late for the specified DX_TIME.
// Remedial Action - (a) cancel delayed send
- temp = (uint8)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
+ temp = (uint8_t)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
// Note event Delayed TX Time too Late
// Could fall through to start a normal send (below) just sending late.....
@@ -2742,7 +2768,7 @@
}
else
{
- temp |= (uint8)SYS_CTRL_TXSTRT ;
+ temp |= (uint8_t)SYS_CTRL_TXSTRT ;
dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
}
@@ -2780,10 +2806,10 @@
void dwt_forcetrxoff(void)
{
decaIrqStatus_t stat ;
- uint8 temp ;
- uint32 mask;
+ uint8_t temp ;
+ uint32_t mask;
- temp = (uint8)SYS_CTRL_TRXOFF ; // This assumes the bit is in the lowest byte
+ temp = (uint8_t)SYS_CTRL_TRXOFF ; // This assumes the bit is in the lowest byte
mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask
@@ -2824,14 +2850,14 @@
*/
void dwt_syncrxbufptrs(void)
{
- uint8 buff ;
+ uint8_t buff ;
// Need to make sure that the host/IC buffer pointers are aligned before starting RX
dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &buff);
if((buff & (SYS_STATUS_ICRBP >> 24)) != // IC side Receive Buffer Pointer
((buff & (SYS_STATUS_HSRBP >> 24)) << 1) ) // Host Side Receive Buffer Pointer
{
- uint8 hsrb = 0x01;
+ uint8_t hsrb = 0x01;
dwt_writetodevice(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET , 1, &hsrb) ; // We need to swap RX buffer status reg (write one to toggle internally)
}
}
@@ -2853,9 +2879,9 @@
*
* no return value
*/
-void dwt_setrxmode(int mode, uint8 rxON, uint8 rxOFF)
+void dwt_setrxmode(int mode, uint8_t rxON, uint8_t rxOFF)
{
- uint16 reg16 = RX_SNIFF_MASK & ((rxOFF << 8) | rxON);
+ uint16_t reg16 = RX_SNIFF_MASK & ((rxOFF << 8) | rxON);
if(mode & DWT_RX_SNIFF)
{
@@ -2883,29 +2909,29 @@
*/
int dwt_rxenable(int delayed)
{
- uint16 temp ;
- uint8 temp1 = 0;
+ uint16_t temp ;
+ uint8_t temp1 = 0;
dwt_syncrxbufptrs();
- temp = (uint16)SYS_CTRL_RXENAB ;
+ temp = (uint16_t)SYS_CTRL_RXENAB ;
if (delayed)
{
- temp |= (uint16)SYS_CTRL_RXDLYE ;
+ temp |= (uint16_t)SYS_CTRL_RXDLYE ;
}
dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, temp) ;
if (delayed) // Check for errors
{
- //uint32 status1 = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register
+ //uint32_t status1 = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register
dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &temp1) ;
if (temp1 & (SYS_STATUS_HPDWARN >> 24)) // If delay has not passed do delayed else immediate RX on
{
dwt_forcetrxoff(); // Turn the delayed receive off, and do immediate receive, return warning indication
- temp = (uint16)SYS_CTRL_RXENAB; // Clear the delay bit
+ temp = (uint16_t)SYS_CTRL_RXENAB; // Clear the delay bit
dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, temp) ;
return DWT_ERROR;
}
@@ -2928,9 +2954,9 @@
*
* no return value
*/
-void dwt_setrxtimeout(uint16 time)
+void dwt_setrxtimeout(uint16_t time)
{
- uint8 temp ;
+ uint8_t temp ;
dwt_readfromdevice(SYS_CFG_ID, 3, 1, &temp) ; // Read register
@@ -2938,7 +2964,7 @@
{
dwt_write16bitoffsetreg(RX_FWTO_ID, 0x0, time) ;
- temp |= (uint8)(SYS_CFG_RXWTOE >> 24);
+ temp |= (uint8_t)(SYS_CFG_RXWTOE >> 24);
// OR in 32bit value (1 bit set), I know this is in high byte.
dw1000local.sysCFGreg |= SYS_CFG_RXWTOE;
@@ -2946,7 +2972,7 @@
}
else
{
- temp &= ~((uint8)(SYS_CFG_RXWTOE >> 24));
+ temp &= ~((uint8_t)(SYS_CFG_RXWTOE >> 24));
// AND in inverted 32bit value (1 bit clear), I know this is in high byte.
dw1000local.sysCFGreg &= ~(SYS_CFG_RXWTOE);
@@ -2970,7 +2996,7 @@
*
* no return value
*/
-void dwt_setpreambledetecttimeout(uint16 timeout)
+void dwt_setpreambledetecttimeout(uint16_t timeout)
{
dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_PRETOC_OFFSET, timeout);
}
@@ -2999,10 +3025,10 @@
*
* no return value
*/
-void dwt_setinterrupt(uint32 bitmask, uint8 enable)
+void dwt_setinterrupt(uint32_t bitmask, uint8_t enable)
{
decaIrqStatus_t stat ;
- uint32 mask ;
+ uint32_t mask ;
// Need to beware of interrupts occurring in the middle of following read modify write cycle
stat = decamutexon() ;
@@ -3035,14 +3061,14 @@
*/
void dwt_configeventcounters(int enable)
{
- uint8 temp = 0x0; //disable
+ uint8_t temp = 0x0; //disable
// Need to clear and disable, can't just clear
- temp = (uint8)(EVC_CLR); // Clear and disable
+ temp = (uint8_t)(EVC_CLR); // Clear and disable
dwt_writetodevice(DIG_DIAG_ID, EVC_CTRL_OFFSET, 1, &temp) ;
if(enable)
{
- temp = (uint8)(EVC_EN); // Enable
+ temp = (uint8_t)(EVC_EN); // Enable
dwt_writetodevice(DIG_DIAG_ID, EVC_CTRL_OFFSET, 1, &temp) ;
}
}
@@ -3061,7 +3087,7 @@
*/
void dwt_readeventcounters(dwt_deviceentcnts_t *counters)
{
- uint32 temp;
+ uint32_t temp;
temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_PHE_OFFSET); // Read sync loss (31-16), PHE (15-0)
counters->PHE = temp & 0xFFF;
@@ -3102,7 +3128,7 @@
*/
void dwt_rxreset(void)
{
- uint8 resetrx = 0xe0;
+ uint8_t resetrx = 0xe0;
// Set RX reset
dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
@@ -3123,7 +3149,7 @@
*/
void dwt_softreset(void)
{
- uint8 temp[1] = {0};
+ uint8_t temp[1] = {0};
_dwt_disablesequencing();
//_dwt_enableclocks(FORCE_SYS_XTI); // Set system clock to XTI
@@ -3164,9 +3190,9 @@
*
* no return value
*/
-void dwt_xtaltrim(uint8 value)
+void dwt_xtaltrim(uint8_t value)
{
- uint8 write_buf;
+ uint8_t write_buf;
dwt_readfromdevice(FS_CTRL_ID, FS_XTALT_OFFSET, 1, &write_buf);
@@ -3190,9 +3216,9 @@
*
* returns DWT_SUCCESS for success, or DWT_ERROR for error
*/
-int dwt_configcwmode(uint8 chan)
+int dwt_configcwmode(uint8_t chan)
{
- uint8 write_buf[1];
+ uint8_t write_buf[1];
#ifdef DWT_API_ERROR_CHECK
if ((chan < 1) || (chan > 7) || (6 == chan))
{
@@ -3254,9 +3280,9 @@
*
* no return value
*/
-void dwt_configcontinuousframemode(uint32 framerepetitionrate)
+void dwt_configcontinuousframemode(uint32_t framerepetitionrate)
{
- uint8 write_buf[4];
+ uint8_t write_buf[4];
//
// Disable TX/RX RF block sequencing (needed for continuous frame mode)
@@ -3284,7 +3310,7 @@
//
// Configure continuous frame TX
//
- write_buf[0] = (uint8)(DIAG_TMC_TX_PSTM) ;
+ write_buf[0] = (uint8_t)(DIAG_TMC_TX_PSTM) ;
dwt_writetodevice(DIG_DIAG_ID, DIAG_TMC_OFFSET, 1, write_buf); // Turn the tx power spectrum test mode - continuous sending of frames
}
@@ -3309,11 +3335,11 @@
*
* returns (temp_raw<<8)|(vbat_raw)
*/
-uint16 dwt_readtempvbat(uint8 fastSPI)
+uint16_t dwt_readtempvbat(uint8_t fastSPI)
{
- uint8 wr_buf[2];
- uint8 vbat_raw;
- uint8 temp_raw;
+ uint8_t wr_buf[2];
+ uint8_t vbat_raw;
+ uint8_t temp_raw;
// These writes should be single writes and in sequence
wr_buf[0] = 0x80; // Enable TLD Bias
@@ -3368,9 +3394,9 @@
*
* returns: 8-bit raw temperature sensor value
*/
-uint8 dwt_readwakeuptemp(void)
+uint8_t dwt_readwakeuptemp(void)
{
- uint8 temp_raw;
+ uint8_t temp_raw;
dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LTEMP_OFFSET, 1, &temp_raw);
return (temp_raw);
}
@@ -3388,9 +3414,9 @@
*
* returns: 8-bit raw battery voltage sensor value
*/
-uint8 dwt_readwakeupvbat(void)
+uint8_t dwt_readwakeupvbat(void)
{
- uint8 vbat_raw;
+ uint8_t vbat_raw;
dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET, 1, &vbat_raw);
return (vbat_raw);
}
--
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