From dd981218e231280601596abd643669556b36c102 Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期日, 27 九月 2020 10:22:52 +0800
Subject: [PATCH] 增加调试信息，调试标签DW芯片状态异常中
---
源码/核心板/Src/decadriver/deca_device.c | 48 +++++++++++++++++++++++++++++++++++++-----------
1 files changed, 37 insertions(+), 11 deletions(-)
diff --git "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c" "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
index 40dfb9c..3825217 100644
--- "a/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
+++ "b/\346\272\220\347\240\201/\346\240\270\345\277\203\346\235\277/Src/decadriver/deca_device.c"
@@ -109,9 +109,12 @@
#define VBAT_ADDRESS (0x08)
#define VTEMP_ADDRESS (0x09)
#define XTRIM_ADDRESS (0x1E)
-
+u8 module_power;
+uint32_t status_reg = 0;
int dwt_initialise(uint16_t config)
{
+
+ u32 power_temp,power_input;
uint8_t plllockdetect = EC_CTRL_PLLLCK;
uint16_t otp_addr = 0;
uint32_t ldo_tune = 0;
@@ -124,24 +127,36 @@
dw1000local.dwt_txcallback = NULL ;
dw1000local.dwt_rxcallback = NULL ;
-
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
+ status_reg = dwt_read32bitreg(SYS_STATUS_ID);
// Read and validate device ID return -1 if not recognised
dw1000local.deviceID = dwt_readdevid() ;
- if (DWT_DEVICE_ID != dw1000local.deviceID) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
+ while (DWT_DEVICE_ID != dw1000local.deviceID) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
{
- return DWT_ERROR ;
+ dw1000local.deviceID = dwt_readdevid() ;
}
-
- _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
-
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
+ // _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
+ status_reg = dwt_read32bitreg(SYS_STATUS_ID);
+ if(module_power>67)
+ {module_power=67;}
+ if(module_power<0)
+ {module_power=0;}
+ if(module_power>36)
+ {
+ power_temp =(module_power-36);
+ }else{
+ power_temp = ((6-(module_power/6))<<5)|(module_power%6);
+ }
+ power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp;
+ dwt_write32bitreg(TX_POWER_ID, power_input);
// Configure the CPLL lock detect
dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
// Read OTP revision number
otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte
-
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
// Load LDO tune from OTP and kick it if there is a value actually programmed.
ldo_tune = _dwt_otpread(LDOTUNE_ADDRESS);
if((ldo_tune & 0xFF) != 0)
@@ -155,7 +170,7 @@
// Load Part and Lot ID from OTP
dw1000local.partID = _dwt_otpread(PARTID_ADDRESS);
dw1000local.lotID = _dwt_otpread(LOTID_ADDRESS);
-
+status_reg = dwt_read32bitreg(SYS_STATUS_ID);
// XTAL trim value is set in OTP for DW1000 module and EVK/TREK boards but that might not be the case in a custom design
dw1000local.xtrim = otp_addr & 0x1F;
if (!dw1000local.xtrim) // A value of 0 means that the crystal has not been trimmed
@@ -165,6 +180,8 @@
// Configure XTAL trim
dwt_xtaltrim(dw1000local.xtrim);
+ status_reg = dwt_read32bitreg(SYS_STATUS_ID);
+
// Load leading edge detect code
if(config & DWT_LOADUCODE)
{
@@ -182,7 +199,16 @@
// Read system register / store local copy
dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
-
+ {
+ uint32_t reg;
+ reg = dwt_read32bitreg(GPIO_CTRL_ID);
+ reg |= 0x00014000;
+ reg |= 0x00050000;
+ dwt_write32bitreg(GPIO_CTRL_ID,reg);
+ dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK);
+
+ }
+ dw1000local.deviceID = dwt_readdevid() ;
return DWT_SUCCESS ;
} // end dwt_initialise()
--
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