From 12ef59c562f0bfa5b7f9f4ac808a7d340adab9de Mon Sep 17 00:00:00 2001
From: yincheng.zhong <634916154@qq.com>
Date: 星期一, 11 三月 2024 14:20:43 +0800
Subject: [PATCH] 微功率版本
---
Src/decadriver/deca_device.c | 67 +++++++++++++++++++++++++++++----
1 files changed, 59 insertions(+), 8 deletions(-)
diff --git a/Src/decadriver/deca_device.c b/Src/decadriver/deca_device.c
index f5269c5..6b8935d 100644
--- a/Src/decadriver/deca_device.c
+++ b/Src/decadriver/deca_device.c
@@ -147,15 +147,33 @@
//
// Spi_ChangePrescaler(SPI_BAUDRATEPRESCALER_8);
//}
+#define DWT_LNA_PA_DISABLE 0x00
+#define DWT_LNA_ENABLE 0x01
+#define DWT_PA_ENABLE 0x02
+void dwt_setlnapamode(int lna_pa)
+{
+ uint32_t gpio_mode = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET);
+ gpio_mode &= ~(GPIO_MSGP4_MASK | GPIO_MSGP5_MASK | GPIO_MSGP6_MASK);
+ if (lna_pa & DWT_LNA_ENABLE)
+ {
+ gpio_mode |= GPIO_PIN6_EXTRXE;
+ }
+ if (lna_pa & DWT_PA_ENABLE)
+ {
+ gpio_mode |= (GPIO_PIN5_EXTTXE | GPIO_PIN4_EXTPA);
+ }
+ dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, gpio_mode);
+}
#define LDOTUNE_ADDRESS (0x04)
#define PARTID_ADDRESS (0x06)
#define LOTID_ADDRESS (0x07)
#define VBAT_ADDRESS (0x08)
#define VTEMP_ADDRESS (0x09)
#define XTRIM_ADDRESS (0x1E)
-
+uint8_t module_power;
int dwt_initialise(uint16_t config)
{
+ uint32_t power_temp,power_input;
uint8_t plllockdetect = EC_CTRL_PLLLCK;
uint16_t otp_addr = 0;
uint32_t ldo_tune = 0;
@@ -177,7 +195,14 @@
}
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+ if(module_power>36)
+ {
+ power_temp =(module_power-36);
+ }else{
+ power_temp = ((6-(module_power/6))<<5)|(module_power%6);
+ }
+ power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp;
+ dwt_write32bitreg(TX_POWER_ID, power_input);
// Configure the CPLL lock detect
dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
// Read OTP revision number
@@ -224,12 +249,13 @@
// Read system register / store local copy
dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
{
- uint32_t reg;
- reg = dwt_read32bitreg(GPIO_CTRL_ID);
- reg |= 0x00014000;
- reg |= 0x00050000;
- dwt_write32bitreg(GPIO_CTRL_ID,reg);
- dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK);
+ dwt_setlnapamode(DWT_LNA_ENABLE);
+// uint32_t reg;
+// reg = dwt_read32bitreg(GPIO_CTRL_ID);
+// reg |= 0x00014000;
+// reg |= 0x00050000;
+// dwt_write32bitreg(GPIO_CTRL_ID,reg);
+// dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK);
}
// CheckCPUID();
@@ -799,7 +825,32 @@
//diagnostics->debug2 = dwt_read32bitoffsetreg(0x27, 0xc);
}
+#define B20_SIGN_EXTEND_TEST (0x00100000UL)
+#define B20_SIGN_EXTEND_MASK (0xFFF00000UL)
+/* offset from DRX_CONF_ID in bytes to 21-bit signed RX carrier integrator value */
+#define DRX_CARRIER_INT_OFFSET 0x28
+#define DRX_CARRIER_INT_LEN (3)
+#define DRX_CARRIER_INT_MASK 0x001FFFFF
+int32_t dwt_readcarrierintegrator(void)
+{
+ uint32_t regval = 0 ;
+ int j ;
+ uint8_t buffer[DRX_CARRIER_INT_LEN] ;
+ /* Read 3 bytes into buffer (21-bit quantity) */
+
+ dwt_readfromdevice(DRX_CONF_ID,DRX_CARRIER_INT_OFFSET,DRX_CARRIER_INT_LEN, buffer) ;
+
+ for (j = 2 ; j >= 0 ; j --) // arrange the three bytes into an unsigned integer value
+ {
+ regval = (regval << 8) + buffer[j] ;
+ }
+
+ if (regval & B20_SIGN_EXTEND_TEST) regval |= B20_SIGN_EXTEND_MASK ; // sign extend bit #20 to whole word
+ else regval &= DRX_CARRIER_INT_MASK ; // make sure upper bits are clear if not sign extending
+
+ return (int32_t) regval ; // cast unsigned value to signed quantity.
+}
/*! ------------------------------------------------------------------------------------------------------------------
* @fn dwt_readtxtimestamp()
*
--
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