From 187d5a216bff2485bb98869e3b96a46ab2e2d808 Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期一, 17 七月 2023 16:54:24 +0800
Subject: [PATCH] 改为dw3000，代码修改结束，没有测试，先提交一下。
---
Src/decadriver/deca_params_init.c | 24 ++++++++++++++++++------
1 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/Src/decadriver/deca_params_init.c b/Src/decadriver/deca_params_init.c
index de4c1d9..e5c5330 100644
--- a/Src/decadriver/deca_params_init.c
+++ b/Src/decadriver/deca_params_init.c
@@ -27,12 +27,12 @@
//-----------------------------------------
const uint32_t tx_config[NUM_CH] =
{
- RF_TXCTRL_CH1, /* Tx value match UM */
- RF_TXCTRL_CH2,
- RF_TXCTRL_CH3,
- RF_TXCTRL_CH4,
+// RF_TXCTRL_CH1, /* Tx value match UM */
+// RF_TXCTRL_CH2,
+// RF_TXCTRL_CH3,
+// RF_TXCTRL_CH4,
RF_TXCTRL_CH5,
- RF_TXCTRL_CH7,
+// RF_TXCTRL_CH7,
};
//RF -> Channel_Specific_Cfg -> Channel_Cfg -> RF_PLL -> RF PLL2
@@ -59,7 +59,19 @@
0xBC //WBW
};
-
+/* offset from AGC_CTRL_ID in bytes */
+/* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
+#define AGC_TUNE1_OFFSET (0x04)
+#define AGC_TUNE1_LEN (2)
+#define AGC_TUNE1_MASK 0xFFFF /* It is a 16-bit tuning register for the AGC. */
+#define AGC_TUNE1_16M 0x8870
+#define AGC_TUNE1_64M 0x889B
+/* offset from AGC_CTRL_ID in bytes */
+/* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
+#define AGC_TUNE2_OFFSET (0x0C)
+#define AGC_TUNE2_LEN (4)
+#define AGC_TUNE2_MASK 0xFFFFFFFFUL
+#define AGC_TUNE2_VAL 0X2502A907UL
const agc_cfg_struct agc_config =
{
AGC_TUNE2_VAL,
--
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