From 20bdb4be1fc4676cceaf09456b5ff4b648f4a4a4 Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期四, 14 七月 2022 15:21:33 +0800
Subject: [PATCH] v2.49 新版子功能调通
---
Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h | 24 +++++++++++++-----------
1 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h
index 6e7e2ca..a50fb96 100644
--- a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h
+++ b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright(c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -571,6 +571,15 @@
/** @addtogroup Exported_constants
* @{
*/
+
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
@@ -2981,7 +2990,9 @@
/* Reset and Clock Control */
/* */
/******************************************************************************/
-
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
/******************** Bit definition for RCC_CR register ********************/
@@ -4697,13 +4708,7 @@
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
*/
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
- || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
-#else
-#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
-#endif
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
@@ -5759,9 +5764,6 @@
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
/******************* TIM Instances : output(s) OCXEC register *****************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
--
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