From 20bdb4be1fc4676cceaf09456b5ff4b648f4a4a4 Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期四, 14 七月 2022 15:21:33 +0800
Subject: [PATCH] v2.49 新版子功能调通
---
Src/stm32l0xx_it.c | 21 ++++++++++++++++-----
1 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/Src/stm32l0xx_it.c b/Src/stm32l0xx_it.c
index 1e6d2fc..ce1d928 100644
--- a/Src/stm32l0xx_it.c
+++ b/Src/stm32l0xx_it.c
@@ -27,7 +27,7 @@
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
-
+extern float motor_keeptime;
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
@@ -61,11 +61,13 @@
extern DMA_HandleTypeDef hdma_usart1_tx;
extern UART_HandleTypeDef huart1;
/* USER CODE BEGIN EV */
-
+float motor_ontime=0;
+uint8_t userkey_state = 0;
+extern u8 active_flag;
/* USER CODE END EV */
/******************************************************************************/
-/* Cortex-M0+ Processor Interruption and Exception Handlers */
+/* Cortex-M0+ Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
@@ -91,6 +93,7 @@
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ //printf("HardFault_Handler.\r\n");
SCB->AIRCR = 0X05FA0000|(unsigned int)0x04;
/* USER CODE END W1_HardFault_IRQn 0 */
}
@@ -149,6 +152,7 @@
void EXTI0_1_IRQHandler(void)
{
/* USER CODE BEGIN EXTI0_1_IRQn 0 */
+ SystemClock_Config();
if(GET_IMUINT)
{
nomove_count = 0;
@@ -156,9 +160,16 @@
if(!GET_USERKEY)
{
+ userkey_state = 1;
+
+ if(g_com_map[MOTOR_ENABLE])
+ {
+ motor_keeptime = 2;
+ }
nomove_count = 0;
- waitusart_timer = tag_frequency*USART_KEEPWAKE_TIME;
- UsartInit();
+// waitusart_timer = tag_frequency*USART_KEEPWAKE_TIME;
+ // UsartInit();
+
// MOTOR_ON;
}
--
Gitblit v1.9.3