From 3e165b6f13bfaf66385d857819cacff6e4d6f37c Mon Sep 17 00:00:00 2001
From: zhyinch <zhyinch@gmail.com>
Date: 星期六, 20 六月 2020 22:31:03 +0800
Subject: [PATCH] 时间同步完成，多基站有问题，时间不对
---
Src/decadriver/deca_device.c | 16 ++++++++++++++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/Src/decadriver/deca_device.c b/Src/decadriver/deca_device.c
index f5269c5..bef3021 100644
--- a/Src/decadriver/deca_device.c
+++ b/Src/decadriver/deca_device.c
@@ -153,9 +153,10 @@
#define VBAT_ADDRESS (0x08)
#define VTEMP_ADDRESS (0x09)
#define XTRIM_ADDRESS (0x1E)
-
+uint8_t module_power;
int dwt_initialise(uint16_t config)
{
+ uint32_t power_temp,power_input;
uint8_t plllockdetect = EC_CTRL_PLLLCK;
uint16_t otp_addr = 0;
uint32_t ldo_tune = 0;
@@ -177,7 +178,18 @@
}
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+ if(module_power>67)
+ {module_power=67;}
+ if(module_power<0)
+ {module_power=0;}
+ if(module_power>36)
+ {
+ power_temp =(module_power-36);
+ }else{
+ power_temp = ((6-(module_power/6))<<5)|(module_power%6);
+ }
+ power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp;
+ dwt_write32bitreg(TX_POWER_ID, power_input);
// Configure the CPLL lock detect
dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
// Read OTP revision number
--
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