From 5634c27b87d185b213dc31c921f9b64e5303d368 Mon Sep 17 00:00:00 2001
From: yincheng.zhong <634916154@qq.com>
Date: 星期一, 22 一月 2024 22:22:41 +0800
Subject: [PATCH] Merge branch '免布线基站-lora' of http://47.108.70.204:60062/r/XRange_Tag into 免布线基站-lora
---
Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h | 46 +++++++++++++++++++++++++---------------------
1 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h
index 1e28ead..8594a64 100644
--- a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h
+++ b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h
@@ -14,13 +14,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright(c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -72,7 +71,7 @@
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
@@ -754,6 +753,15 @@
/** @addtogroup Exported_constants
* @{
*/
+
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
@@ -3286,7 +3294,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -3653,9 +3661,13 @@
/* Reset and Clock Control */
/* */
/******************************************************************************/
-
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+#define RCC_MCO3_SUPPORT /*!<Support MCO3 */
+#define RCC_MCO3_AF0_SUPPORT /*!<Support MCO3 on Alternate Function AF2 */
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (0U)
@@ -4455,7 +4467,7 @@
#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_Pos (16U)
#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
@@ -5605,13 +5617,7 @@
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
*/
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
- || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
-#else
-#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
-#endif
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
@@ -7365,7 +7371,7 @@
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
-/***************** TIM Instances : external trigger input availabe ************/
+/***************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
@@ -7385,9 +7391,6 @@
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
/******************* TIM Instances : output(s) OCXEC register *****************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
@@ -7480,6 +7483,7 @@
#define RCC_IRQn RCC_CRS_IRQn
#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
#define ADC1_IRQn ADC1_COMP_IRQn
+#define SVC_IRQn SVCall_IRQn
/* Aliases for __IRQHandler */
#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
@@ -7506,4 +7510,4 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--
Gitblit v1.9.3