From 5634c27b87d185b213dc31c921f9b64e5303d368 Mon Sep 17 00:00:00 2001
From: yincheng.zhong <634916154@qq.com>
Date: 星期一, 22 一月 2024 22:22:41 +0800
Subject: [PATCH] Merge branch '免布线基站-lora' of http://47.108.70.204:60062/r/XRange_Tag into 免布线基站-lora
---
Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c | 70 ++++++++++++++++-------------------
1 files changed, 32 insertions(+), 38 deletions(-)
diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c b/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c
index 814b0c7..d50e65c 100644
--- a/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c
+++ b/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c
@@ -22,13 +22,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright(c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -77,11 +76,30 @@
*/
/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
- This value must be a multiple of 0x100. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
/******************************************************************************/
/**
* @}
@@ -134,37 +152,14 @@
*/
void SystemInit (void)
{
-/*!< Set MSION bit */
- RCC->CR |= (uint32_t)0x00000100U;
-
- /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
- RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
- /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
- /*!< Reset HSI48ON bit */
- RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
- /*!< Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
- /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
- RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
- /*!< Disable all interrupts */
- RCC->CIER = 0x00000000U;
-
/* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
+#if defined (USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
}
/**
- * @brief Update SystemCoreClock according to Clock Register Values
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
@@ -276,4 +271,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--
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