From 858c42df60ffeb07dc5916e2cec1f0b98b1b4e39 Mon Sep 17 00:00:00 2001
From: yincheng.zhong <634916154@qq.com>
Date: 星期五, 12 五月 2023 12:04:39 +0800
Subject: [PATCH] V2.4 1.修改震动逻辑,先短振3下,5秒后再振3下,每5分钟循环一次,如果短按按键,2小时内不再震动。 2.SOS改成长按3秒按键触发。

---
 Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h |   14 +++++---------
 1 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h
index 8b98906..eba7029 100644
--- a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h
+++ b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h
@@ -3801,9 +3801,13 @@
 /*                         Reset and Clock Control                            */
 /*                                                                            */
 /******************************************************************************/
-
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
 #define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
 #define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
+#define RCC_MCO3_SUPPORT            /*!<Support MCO3 */
+#define RCC_MCO3_AF2_SUPPORT        /*!<Support MCO3 on Alternate Function AF0 */
 
 /********************  Bit definition for RCC_CR register  ********************/
 #define RCC_CR_HSION_Pos                 (0U) 
@@ -5885,13 +5889,8 @@
 /*
 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
 */
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
-    || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
 #define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
 #define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#else
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#endif	
 
 /*******************  Bit definition for TIM_CR1 register  ********************/
 #define TIM_CR1_CEN_Pos           (0U)        
@@ -7709,9 +7708,6 @@
                                          ((INSTANCE) == TIM3)  || \
                                          ((INSTANCE) == TIM21)  || \
                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
 
 /******************* TIM Instances : output(s) OCXEC register *****************/
 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \

--
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