From 89c6ac19c36a4773d406c8b99f355020df031c2c Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期五, 25 八月 2023 17:14:06 +0800
Subject: [PATCH] 版本2.11，修复不能测距的bug

---
 Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h |   15 ++++-----------
 1 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h
index 58fab12..005e8af 100644
--- a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h
+++ b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h
@@ -14,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright(c) 2018 STMicroelectronics.
+  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
@@ -2988,7 +2988,9 @@
 /*                         Reset and Clock Control                            */
 /*                                                                            */
 /******************************************************************************/
-
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
 #define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
 
 /********************  Bit definition for RCC_CR register  ********************/
@@ -4738,13 +4740,7 @@
 /*
 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
 */
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
-    || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
 #define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#else
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#endif	
 
 /*******************  Bit definition for TIM_CR1 register  ********************/
 #define TIM_CR1_CEN_Pos           (0U)        
@@ -5830,9 +5826,6 @@
 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
                                          ((INSTANCE) == TIM21)  || \
                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
 
 /******************* TIM Instances : output(s) OCXEC register *****************/
 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)

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