From 89d1221d104e5283832a871c8c734b7ddb421ddb Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期三, 22 十一月 2023 14:41:44 +0800
Subject: [PATCH] 未修改完成，先提交。防撞测距正常，改为1024前导码，并加入LDE抗反射。
---
Src/decadriver/deca_device.c | 37 +++++++++++++++++++++++++++++++++++--
1 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/Src/decadriver/deca_device.c b/Src/decadriver/deca_device.c
index f5269c5..05d4ff0 100644
--- a/Src/decadriver/deca_device.c
+++ b/Src/decadriver/deca_device.c
@@ -153,9 +153,10 @@
#define VBAT_ADDRESS (0x08)
#define VTEMP_ADDRESS (0x09)
#define XTRIM_ADDRESS (0x1E)
-
+uint8_t module_power;
int dwt_initialise(uint16_t config)
{
+ uint32_t power_temp,power_input;
uint8_t plllockdetect = EC_CTRL_PLLLCK;
uint16_t otp_addr = 0;
uint32_t ldo_tune = 0;
@@ -177,7 +178,14 @@
}
_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
- dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
+ if(module_power>36)
+ {
+ power_temp =(module_power-36);
+ }else{
+ power_temp = ((6-(module_power/6))<<5)|(module_power%6);
+ }
+ power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp;
+ dwt_write32bitreg(TX_POWER_ID, power_input);
// Configure the CPLL lock detect
dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);
// Read OTP revision number
@@ -3446,7 +3454,32 @@
return (vbat_raw);
}
+#define B20_SIGN_EXTEND_TEST (0x00100000UL)
+#define B20_SIGN_EXTEND_MASK (0xFFF00000UL)
+/* offset from DRX_CONF_ID in bytes to 21-bit signed RX carrier integrator value */
+#define DRX_CARRIER_INT_OFFSET 0x28
+#define DRX_CARRIER_INT_LEN (3)
+#define DRX_CARRIER_INT_MASK 0x001FFFFF
+int32_t dwt_readcarrierintegrator(void)
+{
+ uint32_t regval = 0 ;
+ int j ;
+ uint8_t buffer[DRX_CARRIER_INT_LEN] ;
+ /* Read 3 bytes into buffer (21-bit quantity) */
+
+ dwt_readfromdevice(DRX_CONF_ID,DRX_CARRIER_INT_OFFSET,DRX_CARRIER_INT_LEN, buffer) ;
+
+ for (j = 2 ; j >= 0 ; j --) // arrange the three bytes into an unsigned integer value
+ {
+ regval = (regval << 8) + buffer[j] ;
+ }
+
+ if (regval & B20_SIGN_EXTEND_TEST) regval |= B20_SIGN_EXTEND_MASK ; // sign extend bit #20 to whole word
+ else regval &= DRX_CARRIER_INT_MASK ; // make sure upper bits are clear if not sign extending
+
+ return (int32_t) regval ; // cast unsigned value to signed quantity.
+}
/* ===============================================================================================
List of expected (known) device ID handled by this software
===============================================================================================
--
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