From a9357d6172cb307dc8a6b4740f643bd3c0cded55 Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期四, 20 七月 2023 18:15:29 +0800
Subject: [PATCH] 开发完毕，使用前需要重新安排一下代码。
---
Src/decadriver/deca_device.c | 8 +++++---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/Src/decadriver/deca_device.c b/Src/decadriver/deca_device.c
index 9b81fb8..4450202 100644
--- a/Src/decadriver/deca_device.c
+++ b/Src/decadriver/deca_device.c
@@ -63,10 +63,10 @@
*/
decaIrqStatus_t decamutexon(void)
{
- decaIrqStatus_t s = HAL_GPIO_ReadPin(GPIOA,GPIO_PIN_0);
+ decaIrqStatus_t s = HAL_GPIO_ReadPin(GPIOB,GPIO_PIN_8);
if(s) {
- HAL_NVIC_DisableIRQ(EXTI0_1_IRQn);
+ HAL_NVIC_DisableIRQ(EXTI4_15_IRQn);
// NVIC_DisableIRQ(EXTI0_1_IRQn); //disable the external interrupt line
}
return s ; // return state before disable, value is used to re-enable in decamutexoff call
@@ -90,7 +90,7 @@
void decamutexoff(decaIrqStatus_t s) // put a function here that re-enables the interrupt at the end of the critical section
{
if(s) { //need to check the port state as we can't use level sensitive interrupt on the STM ARM
- HAL_NVIC_EnableIRQ(EXTI0_1_IRQn);
+ HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
}
}
@@ -3366,11 +3366,13 @@
*
* return value is 1 if the IDLE_RC bit is set and 0 otherwise
*/
+uint32_t reg1111;
uint8_t dwt_checkidlerc(void)
{
//deca_sleep(2); /* wait 2 ms for DW IC to get into IDLE_RC state */
/* Poll DW IC until IDLE_RC event set. This means that DW IC is in IDLE_RC state and ready */
uint32_t reg = ((uint32_t)dwt_read16bitoffsetreg(SYS_STATUS_ID, 2) << 16);
+ uint32_t reg1111 = ((uint32_t)dwt_read16bitoffsetreg(SYS_STATUS_ID, 2) << 16);
return ( (reg & (SYS_STATUS_RCINIT_BIT_MASK)) == (SYS_STATUS_RCINIT_BIT_MASK));
}
--
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