//*** <<< Use Configuration Wizard in Context Menu >>> ***

#ifndef SAMPLE_CONFIG_H
#define SAMPLE_CONFIG_H

// <h> APP and MCU Config
/* System main frequency, Unit M */
// <o> System Clock      <48=> 48M      <32=> 32M
#define CONFIG_SYSTEM_CLOCK                   32
// <i> System main frequency, Unit M

/* Peripherals frequency divide, It can only be even numbers  */
// <o> Periph Divide   <0=> 0    <2=> 2    <4=> 4    <6=> 6    <8=> 8    <10=> 10
#define CONFIG_PERIPH_DIVIDE                  2
// <i> Peripherals frequency divide, It can only be even numbers

/* Enable DCDC Mode */
// <q> Enable DCDC (if disabled means LDO mode)
#define CONFIG_SOC_DCDC_PAN1070                     1
// <i> Enable DCDC (if disabled means LDO mode)

/* FreeRTOS Heap Usage Print*/
// <q> FreeRTOS Heap Usage Print
#define CONFIG_FREERTOS_HEAP_PRINT            0
// <i> FreeRTOS Heap Usage Print

/*vector table remap to ram */
// <q> Vector Remap to Ram
#define CONFIG_VECTOR_REMAP_TO_RAM            1
// <i> vector remap to ram

/*system watch dog enable */
// <q> System Watch Dog Enable
#define CONFIG_SYSTEM_WATCH_DOG_ENABLE            0
// <i> System Watch Dog Enable


/* App Use Ram Function */
// <q> RAM Function
#define CONFIG_RAM_FUNCTION                    1
// <i> adding parts of ram function can improve running ability

#if CONFIG_RAM_FUNCTION
#define CONFIG_RAM_CODE __attribute__((section(".ramfunc")))
#else
#define CONFIG_RAM_CODE
#endif

/* Log enable */
// <q> Log Enable
#define CONFIG_LOG_ENABLE                     1
// <i> Log enable


/* Flash LDO Config */
//<e> Flash LDO Config
// <q> Flash LDO Enable
#define CONFIG_FLASH_LDO_EN                   1
// <i> Flash LDO enable

// <o> Flash LDO Voltage Select
//  <i> default:None => Flash LDO Voltage from FT Info
//    <0=>1.5V
//    <1=>1.6V
//    <2=>1.7V
//    <3=>1.8V
//    <4=>1.9V
//    <5=>2.0V
//    <6=>2.1V
//    <7=>2.2V
//    <8=>None
#define CONFIG_FLASH_LDO_VOL                   8
//</e>


// </h>


// <h> BLE Stack Config

/* user chip unique mac address */
// <q> Use Chip unique Mac Address
#define CONFIG_USER_CHIP_MAC_ADDR                      1
// <i> Use Chip unique Mac Address


/* Select a low-speed clock source  */
// <o> Low-Speed Clock   <0=> RCL    <1=> XTL  <2=> ACT32K
#define CONFIG_LOW_SPEED_CLOCK_SRC            2
// <i> Select a low-speed clock source

/* CENTRAL maximum number of states supported */
// <o> BT_MAX_NUM_OF_CENTRAL
#define CONFIG_BT_MAX_NUM_OF_CENTRAL            1
// <i> CENTRAL maximum number of states supported

/* PERIPHERAL maximum number of states supported */
// <o> BT_MAX_NUM_OF_PERIPHERAL
#define CONFIG_BT_MAX_NUM_OF_PERIPHERAL         1
// <i> PERIPHERAL maximum number of states supported

/* Select BLE TX POWER  */
// <o> TX Power   <0=> 0dBm    <1=> 1dBm    <2=> 2dBm    <3=> 3dBm   <4=> 4dBm   <5=> 5dBm  <6=> 6dBm  <7=> 7dBm <8=> 8dBm <9=> 9dBm
#define CONFIG_BT_CTLR_TX_POWER_DFT           0
// <i> Select BLE TX POWER

/* Force manual calibration of the RCL clock  */
// <q> Force Calib RCL
#define CONFIG_FORCE_CALIB_RCL_CLK            0
// <i> Force manual calibration of the RCL clock, production chips do not need to be turned on

/* BT controller Memory Pool usage print*/
// <q> BT controller Memory Pool usage print
#define CONFIG_CNTRL_MEM_POOL_PRINT            0
// <i> BT controller Memory Pool usage print

/* BT AGC Init Mode*/
// <o> BT AGC Init Mode
#define CONFIG_BT_CTLR_AGC_MODE            0
// <i> BT AGC Init Mode

/* BT Debug Pin Init*/
// <q> BT Debug Pin Init
#define CONFIG_BT_CTLR_LINK_LAYER_DEBUG            0
// <i> BT Debug Pin Init

/* Calib RF Frequency offset*/
// <q> Calib RF Frequency offset
#define CONFIG_RF_CALIB                     0
// <i> Calib RF Frequency offset

// </h>

// <h> Low Power Config
/* low power enable */
// <q> Low Power Enable
#define CONFIG_PM                      0
// <i> low power enable

// <q> Keep Flash Power in Low Power Mode
#define CONFIG_KEEP_FLASH_POWER_IN_LP_MODE    0
// <i> Select this means flash power would be retained in Low Power Mode, and
// <i> there would be a little avg-current increase (about 1uA). The benefit is that
// <i> the large peak current (>15mA) would not occur.

// <q> Enable DeepSleep Mode 2
#define CONFIG_DEEPSLEEP_MODE_2         0
// <i> Enable DeepSleep Mode 2 (Only LPLDOH in use), and the HW APB Timer Wakeup
// <i> and PWM waveform output can be use in this mode.

// <o> Increase LPLDOH trim value   <0=> +0   <1=> +1   <2=> +2   <3=> +3   <4=> +4   <5=> +5   <6=> +6   <7=> +7   <8=> +8
#define CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE       0
// <i> Increase LPLDOH voltage for specific LowPower scenario use.

// <q> Continue Run After Standby M1 Wakeup
#define CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET   0
// <i> Check this configuration to let CPU continue run after standby M1 waking up,
// <i> or CPU would reset after waking up from standby M1.

// <q> Detecting Temperature Optimize Param Enable
#define CONFIG_AUTO_OPTIMIZE_POWER_PARAM     0

/* ADC temperature sample interval(s)*/
// <o> Temperature Sample Interval
#define CONFIG_TEMP_SAMPLE_INTERVAL_S            300
// <i> ADC temperature sample interval(s)

/* DCDC vol */
// <q> DVDD Voltage Optimize Enable
#define CONFIG_DVDD_VOL_OPTIMIZE_EN           0

// <q> HCLK Optimize Enable
#define CONFIG_HCLK_OPTIMIZE_EN              0
// </h>

// <h> Flash Settings Config
/* Flash Settings(kv_store) Start Address*/
// <o> Flash Settings(kv_store) Start Address
#define CONFIG_SETTINGS_START_ADDR         0x6D000
// <i> Flash Settings(kv_store) Start Address

/* Flash Settings(kv_store) Sector Number*/
// <o> Flash Settings(kv_store) Sector Number (>=2)
#define CONFIG_SETTINGS_SECTOR_NUM         2
// <i> Flash Settings(kv_store) Sector Number
// </h>
#endif // SAMPLE_CONFIG_H

//*** <<< end of configuration section >>>    ***