/*
 * Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
 * its subsidiaries and affiliates (collectly called MKSEMI).
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form, except as embedded into an MKSEMI
 *    integrated circuit in a product or a software update for such product,
 *    must reproduce the above copyright notice, this list of conditions and
 *    the following disclaimer in the documentation and/or other materials
 *    provided with the distribution.
 *
 * 3. Neither the name of MKSEMI nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * 4. This software, with or without modification, must only be used with a
 *    MKSEMI integrated circuit.
 *
 * 5. Any software provided in binary form under this license must not be
 *    reverse engineered, decompiled, modified and/or disassembled.
 *
 * THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef MK_DMA_H_
#define MK_DMA_H_
#include "mk_common.h"

/**
 * @addtogroup MK8000_DMA
 * @{
 */

#define DMA_INT_TYPE_ABORT 1       /*!< DMA abort status */
#define DMA_INT_TYPE_ERROR 2       /*!< DMA error status */
#define DMA_INT_TYPE_DONE 3        /*!< DMA done status  */
#define DMA_INT_TYPE_FORCE_ABORT 4 /*!< DMA force abort status  */

/**
 * @brief DMA device IDs enumeration
 */
enum DMA_DEV_T
{
    DMA_ID0 = 0,
    DMA_MAX_NUM
};

/**
 * @brief DMA Channels definition.
 * @note Avoid multiple peripherals DMA requests mapped on the same channel of DMA.
 */
enum DMA_CH_T
{
    DMA_CH0 = 0, /*!< SPI0-RX DMA requests mapped on DMA channel 0 */
    DMA_CH1,     /*!< ADC or SPI0-TX DMA requests mapped on DMA channel 1 */
    DMA_CH2,     /*!< AES-IN/FLASH-WRITE/SPI1-RX DMA requests mapped on DMA channel 2 */
    DMA_CH3,     /*!< AES-OUT/FLASH-READ/SPI1-TX DMA requests mapped on DMA channel 3 */
    DMA_CH4,     /*!< UART0-RX DMA requests mapped on DMA channel 4 */
    DMA_CH5,     /*!< UART0-TX DMA requests mapped on DMA channel 5 */
    DMA_CH6,     /*!< UART1-TX DMA requests mapped on DMA channel 6 */
    DMA_CH7,     /*!< UART1-TX DMA requests mapped on DMA channel 7 */
    DMA_CH_NUM,
};

/**
 * @brief DMA FIFO threshold value.
 * @note DMA FIFO space >= DMA_FF_TH, DMA will start to transfer data from source to FIFO.
 *       The number of valid data in DMA FIFO >= DMA_FF_TH, the DMA will start to pop out data from FIFO to the destination.
 */
enum DMA_FIFO_TH_T
{
    DMA_FIFO_TH_1 = 0, /*!< FIFO threshold value is 1  */
    DMA_FIFO_TH_2,     /*!< FIFO threshold value is 2  */
    DMA_FIFO_TH_4,     /*!< FIFO threshold value is 4  */
    DMA_FIFO_TH_8,     /*!< FIFO threshold value is 8  */
    DMA_FIFO_TH_16,    /*!< FIFO threshold value is 16 */
};

/**
 * @brief DMA burst size definition.
 * @note Burst size are set according to the size of the peripheral buffer being accessed.
 */
enum DMA_SRC_BURST_SIZE_T
{
    DMA_SRC_BURST_SIZE_1 = 0,
    DMA_SRC_BURST_SIZE_4,
    DMA_SRC_BURST_SIZE_8,
    DMA_SRC_BURST_SIZE_16,
    DMA_SRC_BURST_SIZE_32,
    DMA_SRC_BURST_SIZE_64,
    DMA_SRC_BURST_SIZE_128,
    DMA_SRC_BURST_SIZE_256,
};

/**
 * @brief DMA memory/peripheral data width.
 *
 */
enum DMA_WIDTH_T
{
    DMA_WIDTH_1B = 0, /*!< Data aligned by byte     */
    DMA_WIDTH_2B,     /*!< Data aligned by halfword */
    DMA_WIDTH_4B      /*!< Data aligned by word     */
};

/**
 * @brief DMA SRC/DEST address control mode.
 */
enum DMA_ADDR_CTRL_T
{
    DMA_ADDR_INC = 0, /*!< ADDR increment mode */
    DMA_ADDR_DEC,     /*!< ADDR decrement mode */
    DMA_ADDR_FIXED,   /*!< ADDR fixed mode     */
};

/**
 * @brief DMA source request definition.
 */
enum DMA_REQ_SEL_T
{
    DMA_REQ_MEM = 0x00,
    DMA_REQ_SPI0_RX = 0x10,
    DMA_REQ_SPI0_TX = 0x11,
    DMA_REQ_SPI1_RX = 0x12,
    DMA_REQ_SPI1_TX = 0x13,
    DMA_REQ_FLASH = 0x14,
    DMA_REQ_AES_RX = 0x15,
    DMA_REQ_AES_TX = 0x16,
    DMA_REQ_UART0_RX = 0x17,
    DMA_REQ_UART0_TX = 0x18,
    DMA_REQ_UART1_RX = 0x19,
    DMA_REQ_UART1_TX = 0x1A,
    DMA_REQ_ADC = 0x1B,
};

/**
 * @brief DMA channel configure Structure
 */
struct DMA_CH_CFG_T
{
    enum DMA_FIFO_TH_T fifo_th; /*!< Specifies the FIFO threshold level.
                                     This parameter can be a value of @ref DMA_FIFO_TH_T */

    enum DMA_SRC_BURST_SIZE_T src_burst_size; /*!< Specifies the Burst transfer configuration.
                                                   This parameter can be a value of @ref DMA_SRC_BURST_SIZE_T */
    enum DMA_WIDTH_T src_width;               /*!< Specifies the source data width.
                                                   This parameter can be a value of @ref DMA_WIDTH_T */
    enum DMA_WIDTH_T dst_width;               /*!< Specifies the destination data width.
                                                   This parameter can be a value of @ref DMA_WIDTH_T */
    enum DMA_ADDR_CTRL_T src_addr_ctrl;       /*!< Specifies the source address control mode.
                                                   This parameter can be a value of @ref DMA_ADDR_CTRL_T */
    enum DMA_ADDR_CTRL_T dst_addr_ctrl;       /*!< Specifies the destination address control mode.
                                                   This parameter can be a value of @ref DMA_ADDR_CTRL_T */
    enum DMA_REQ_SEL_T src_req_sel;           /*!< Specifies the source request dev
                                                   This parameter can be a value of @ref DMA_REQ_SEL_T */
    enum DMA_REQ_SEL_T dst_req_sel;           /*!< Specifies the destination request dev
                                                   This parameter can be a value of @ref DMA_REQ_SEL_T*/
};

struct DMA_HANDLE_T
{
    DMA_TypeDef *const base;                   /*!< DMA registers base address  */
    const IRQn_Type irq;                       /*!< DMA interrupt number        */
    drv_callback_t callback[DMA_CH_NUM];       /*!< Callback function provided by the user */
    drv_callback_t abort_callback[DMA_CH_NUM]; /*!< DMA abort callback function provided by the user */
};

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief Function for initializing the DMA.
 *
 * @param[in] ch            Enables the specified DMA channel
 * @param[in] config        Pointer to a DMA_CH_CFG_T structure that contains the configuration information for DMA.
 * @return
 *         @arg DEV_ERROR   error id
 *         @arg DEV_OK      Operation is successful
 */
int dma_open(enum DMA_CH_T ch, struct DMA_CH_CFG_T *config);

/**
 * @brief Function for uninitializing the DMA.
 *
 * @param[in] ch            Disables the specified DMA channel
 * @return
 *         @arg DEV_ERROR   error id
 *         @arg DEV_OK      Operation is successful
 */
int dma_close(enum DMA_CH_T ch);

/**
 * @brief Starts the DMA transfer.
 *
 * @param[in] ch            Specifies the DMA channel
 * @param[in] src_addr      The source memory Buffer address
 * @param[out] dst_addr     The destination memory Buffer address
 * @param[in] size          The length of data to be transferred from source to destination
 * @param[in] callback      Callback function provided by the user.
 * @return
 *         @arg DEV_ERROR   error id
 *         @arg DEV_BUSY    DMA process is ongoing
 *         @arg DEV_OK      Operation is successful
 */
int dma_transfer(enum DMA_CH_T ch, void *src_addr, void *dst_addr, uint32_t size, drv_callback_t callback);

/**
 * @brief Stop the DMA transfer.
 *
 * @param[in] ch            Specifies the DMA channel
 * @param[in] callback      Callback function provided by the user.
 * @note If the dma channel is idle, this abort operation is a no-op and the callback function will not be called.
 * @return
 *         @arg DEV_ERROR   error id
 *         @arg DEV_OK      Operation is successful
 */
int dma_abort(enum DMA_CH_T ch, drv_callback_t callback);

/**
 * @brief Force stop DMA transfer.
 *
 * @param[in] ch            Specifies the DMA channel
 * @param[in] callback      Callback function provided by the user.
 * @note This function will force clear any pending DMA interrupt requests.
 */
void dma_force_abort(enum DMA_CH_T ch, drv_callback_t callback);

/**
 * @brief Function for Interrupt handler for DMA.
 */
void DMA_IRQHandler(void);
/**
 * @brief Function for return cndtr for DMA of uart1 rx.
 */
uint32_t get_uart1_dma_cndtr(void);
/**
 * @brief Function for return cndtr for DMA of uart0 rx.
 */
uint32_t get_uart0_dma_cndtr(void);
#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* MK_DMA_H_ */