/*
 * Copyright (c) 2019-2023 Mauna Kea Semiconductor Holdings.
 * All rights reserved.
 *
 */
#ifndef USER_CONFIG_H_
#define USER_CONFIG_H_

/* =========================================================================================================================== */
/* ================                                  Silicon configuration                                    ================ */
/* =========================================================================================================================== */

/** CPU model */
#define CPU_MK8000

/** Enable trace output */
#define TRACE_EN (0)

#define BOR_EN (0)

#define DCDC_EN (0)
/** Configure system clock source @ref enum CLOCK_ATTACH_TYPE_T */
#define SYS_CLK_SOURCE (CLOCK_62P4M_XTAL38P4M_TO_SYS_CLK)

/** AHBCLK = SYSCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
#define AHB_DIV (CLOCK_DIVIDED_BY_1)

/** APBCLK = AHBCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
#define APB_DIV (CLOCK_DIVIDED_BY_1)

/** Configure 32K clock source @ref enum CLOCK_ATTACH_TYPE_T */
#if XTAL32K_EN
#define CLK_32K_SOURCE (CLOCK_XTAL32K_TO_32K_CLK)
#define LOW_POWER_CLOCK_PPM (50)
#else
#define CLK_32K_SOURCE (CLOCK_RCO32K_TO_32K_CLK)
#define LOW_POWER_CLOCK_PPM (1000)
#endif
#define SYS_TICK_EN (1)

#endif /* USER_CONFIG_H_ */