/*
 * Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
 * its subsidiaries and affiliates (collectly called MKSEMI).
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form, except as embedded into an MKSEMI
 *    integrated circuit in a product or a software update for such product,
 *    must reproduce the above copyright notice, this list of conditions and
 *    the following disclaimer in the documentation and/or other materials
 *    provided with the distribution.
 *
 * 3. Neither the name of MKSEMI nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * 4. This software, with or without modification, must only be used with a
 *    MKSEMI integrated circuit.
 *
 * 5. Any software provided in binary form under this license must not be
 *    reverse engineered, decompiled, modified and/or disassembled.
 *
 * THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "mk_dma.h"
#include "mk_clock.h"
#include "mk_reset.h"
#include "mk_trace.h"

static struct DMA_HANDLE_T dma_handle[DMA_MAX_NUM] = {
    {
        .base = DMA,
        .irq = DMA_IRQn,
    },
};

int dma_open(enum DMA_CH_T ch, struct DMA_CH_CFG_T *config)
{
    if ((ch >= DMA_CH_NUM) || (config == NULL))
    {
        return DRV_ERROR;
    }

    if ((dma_handle[DMA_ID0].base->CTRL0 & DMA_CTRL0_ENABLE_MSK) == 0)
    {
        // enable DMA clock
        clock_enable(CLOCK_DMA);
        reset_module(RESET_MODULE_DMA);

        // enable DMA
        dma_handle[DMA_ID0].base->CTRL0 |= DMA_CTRL0_ENABLE_MSK;

        NVIC_SetPriority(dma_handle[DMA_ID0].irq, IRQ_PRIORITY_HIGH);
        NVIC_ClearPendingIRQ(dma_handle[DMA_ID0].irq);
        NVIC_EnableIRQ(dma_handle[DMA_ID0].irq);
    }

    dma_handle[DMA_ID0].base->CH[ch].CFG = DMA_CH_CFG_DST_REQ_SEL(config->dst_req_sel) | DMA_CH_CFG_SRC_REQ_SEL(config->src_req_sel);

    dma_handle[DMA_ID0].base->CH[ch].CTRL = DMA_CH_CTRL_FIFO_TH(config->fifo_th) | DMA_CH_CTRL_SRC_BURST_SIZE(config->src_burst_size) |
                                            DMA_CH_CTRL_SRC_DATA_WIDTH(config->src_width) | DMA_CH_CTRL_DST_DATA_WIDTH(config->dst_width) |
                                            DMA_CH_CTRL_MODE_MSK | DMA_CH_CTRL_SRC_ADDR_CTRL(config->src_addr_ctrl) |
                                            DMA_CH_CTRL_DST_ADDR_CTRL(config->dst_addr_ctrl);

    return DRV_OK;
}

int dma_close(enum DMA_CH_T ch)
{
    if (ch >= DMA_CH_NUM)
    {
        return DRV_ERROR;
    }

    dma_handle[DMA_ID0].base->CH[ch].CTRL &= ~DMA_CH_CTRL_EN_MSK;

    if ((dma_handle[DMA_ID0].base->STATUS1 & DMA_STATUS1_ENABLE_MSK) == 0)
    {
        // disable DMA
        dma_handle[DMA_ID0].base->CTRL0 &= ~DMA_CTRL0_ENABLE_MSK;
        // disable DMA clock
        clock_disable(CLOCK_DMA);

        NVIC_DisableIRQ(dma_handle[DMA_ID0].irq);
        NVIC_ClearPendingIRQ(dma_handle[DMA_ID0].irq);
    }
    return DRV_OK;
}
uint32_t get_uart1_dma_cndtr(void)
{
return dma_handle[DMA_ID0].base->CH[6].DATA_SIZE;
}
uint32_t get_uart0_dma_cndtr(void)
{
return dma_handle[DMA_ID0].base->CH[4].DATA_SIZE;
}

int dma_transfer(enum DMA_CH_T ch, void *src_addr, void *dst_addr, uint32_t size, drv_callback_t callback)
{
    ASSERT(dst_addr, "Invalid transfer dst addr");

    if (dma_handle[DMA_ID0].base->STATUS1 & (1U << (ch + DMA_STATUS1_ENABLE_POS)))
    {
        return DRV_BUSY;
    }

    dma_handle[DMA_ID0].callback[ch] = callback;

    // enable dma channel int
    dma_handle[DMA_ID0].base->CH[ch].CFG &= ~(DMA_CH_CFG_INT_DONE_MSK | DMA_CH_CFG_INT_ERR_MSK | DMA_CH_CFG_INT_ABORT_MSK);

    // source address
    dma_handle[DMA_ID0].base->CH[ch].ADDR_SRC = (uint32_t)src_addr;

    // destination address
    dma_handle[DMA_ID0].base->CH[ch].ADDR_DST = (uint32_t)dst_addr;

    // transfer size
    dma_handle[DMA_ID0].base->CH[ch].DATA_SIZE = size;

    // enable dma channel
    dma_handle[DMA_ID0].base->CH[ch].CTRL |= DMA_CH_CTRL_EN_MSK;

    return DRV_OK;
}

int dma_abort(enum DMA_CH_T ch, drv_callback_t callback)
{
    int ret = DRV_ERROR;
    uint32_t lock = int_lock();
    // Detect whether dma is in a busy state. If it is not in a busy state,
    // abort will not be executed and callback will not be called
    if (REG_IS_BIT_SET(dma_handle[DMA_ID0].base->STATUS1, (1U << (ch + DMA_STATUS1_ENABLE_POS))))
    {
        // disable dma channel done and err int
        dma_handle[DMA_ID0].base->CH[ch].CFG |= (DMA_CH_CFG_INT_DONE_MSK | DMA_CH_CFG_INT_ERR_MSK);
        // Transaction abort
        dma_handle[DMA_ID0].base->CH[ch].CTRL |= DMA_CH_CTRL_ABORT_MSK;

        // Clear Status0 Register
        dma_handle[DMA_ID0].base->INTR_CLR = ((1U << (ch + DMA_INTR_STATUS_DONE_POS)) | (1U << (ch + DMA_INTR_STATUS_ERR_POS)));
        dma_handle[DMA_ID0].abort_callback[ch] = callback;
        ret = DRV_OK;
    }

    int_unlock(lock);
    // LOG_INFO(TRACE_MODULE_DRIVER, "dma_abort %d\r\n", ch);
    return ret;
}

void dma_force_abort(enum DMA_CH_T ch, drv_callback_t callback)
{
    uint32_t lock = int_lock();
    // disable dma channel done/abort/err int
    dma_handle[DMA_ID0].base->CH[ch].CFG |= (DMA_CH_CFG_INT_ABORT_MSK | DMA_CH_CFG_INT_DONE_MSK | DMA_CH_CFG_INT_ERR_MSK);

    if (REG_IS_BIT_SET(dma_handle[DMA_ID0].base->STATUS1, (1U << (ch + DMA_STATUS1_ENABLE_POS))))
    {
        // Transaction abort
        dma_handle[DMA_ID0].base->CH[ch].CTRL |= DMA_CH_CTRL_ABORT_MSK;
    }

    // Clear interrupt penging source
    dma_handle[DMA_ID0].base->INTR_CLR =
        (1U << (ch + DMA_INTR_STATUS_DONE_POS)) | (1U << (ch + DMA_INTR_STATUS_ERR_POS)) | (1U << (ch + DMA_INTR_STATUS_ABORT_POS));
    // Clear interrupt pending
    NVIC_ClearPendingIRQ(dma_handle[DMA_ID0].irq);

    if (callback)
    {
        callback(&ch, DMA_INT_TYPE_FORCE_ABORT);
    }

    int_unlock(lock);
}

void DMA_IRQHandler(void)
{
    uint32_t err_code = 0;
    uint32_t int_status = dma_handle[DMA_ID0].base->INTR_STATUS;

    for (uint8_t i = 0; i < DMA_CH_NUM; i++)
    {
        // abort/error/done interrupt process
        if (int_status & (1U << (i + DMA_INTR_STATUS_ABORT_POS)))
        {
            dma_handle[DMA_ID0].base->INTR_CLR = (1U << (i + DMA_INTR_STATUS_ABORT_POS));
            err_code = DMA_INT_TYPE_ABORT;
        }
        else if (int_status & (1U << (i + DMA_INTR_STATUS_ERR_POS)))
        {
            dma_handle[DMA_ID0].base->INTR_CLR = (1U << (i + DMA_INTR_STATUS_ERR_POS));
            err_code = DMA_INT_TYPE_ERROR;
        }
        else if (int_status & (1U << (i + DMA_INTR_STATUS_DONE_POS)))
        {
            dma_handle[DMA_ID0].base->INTR_CLR = (1U << (i + DMA_INTR_STATUS_DONE_POS));
            err_code = DMA_INT_TYPE_DONE;
        }

        if (err_code == DMA_INT_TYPE_DONE || err_code == DMA_INT_TYPE_ERROR)
        {
            if (dma_handle[DMA_ID0].callback[i])
            {
                dma_handle[DMA_ID0].callback[i](&i, err_code);
            }
            err_code = 0;
        }
        else if (err_code == DMA_INT_TYPE_ABORT)
        {
            if (dma_handle[DMA_ID0].abort_callback[i])
            {
                dma_handle[DMA_ID0].abort_callback[i](&i, err_code);
            }
            err_code = 0;
        }
    }
}