/*
 * Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
 * its subsidiaries and affiliates (collectly called MKSEMI).
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form, except as embedded into an MKSEMI
 *    integrated circuit in a product or a software update for such product,
 *    must reproduce the above copyright notice, this list of conditions and
 *    the following disclaimer in the documentation and/or other materials
 *    provided with the distribution.
 *
 * 3. Neither the name of MKSEMI nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * 4. This software, with or without modification, must only be used with a
 *    MKSEMI integrated circuit.
 *
 * 5. Any software provided in binary form under this license must not be
 *    reverse engineered, decompiled, modified and/or disassembled.
 *
 * THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "mk_gpio.h"
#include "mk_clock.h"
#include "mk_reset.h"
#include "mk_trace.h"

struct GPIO_HANDLE_T
{
    GPIO_TypeDef *const base;
    const IRQn_Type irq;
    uint32_t irq_mask;
    GPIO_IRQ_HANDLER_T irq_handler[IO_PIN_MAX];
};

static struct GPIO_HANDLE_T gpio_handle[GPIO_MAX_NUM] = {
    {
        .base = GPIO,
        .irq = GPIO_IRQn,
        .irq_mask = 0,
        .irq_handler = {0},
    },
};

int gpio_open(void)
{
    // enable GPIO clock
    clock_enable(CLOCK_GPIO);
    reset_module(RESET_MODULE_GPIO);
    return DRV_OK;
}

int gpio_close(void)
{
    // disable GPIO clock
    clock_disable(CLOCK_GPIO);
    return DRV_OK;
}

void gpio_write(uint32_t value)
{
    gpio_handle[0].base->DATAOUT = value;
}

uint32_t gpio_read(void)
{
    return gpio_handle[0].base->DATA;
}

void gpio_pin_set(enum IO_PIN_T pin)
{
    gpio_handle[0].base->DATAOUT = gpio_handle[0].base->DATAOUT | (1U << pin);
}

void gpio_pin_clr(enum IO_PIN_T pin)
{
    gpio_handle[0].base->DATAOUT = gpio_handle[0].base->DATAOUT & (~(1U << pin));
}

void gpio_pin_toggle(enum IO_PIN_T pin)
{
    gpio_handle[0].base->DATAOUT = gpio_handle[0].base->DATAOUT ^ (1U << pin);
}

uint8_t gpio_pin_get_val(enum IO_PIN_T pin)
{
    return (((gpio_handle[0].base->DATA) >> pin) & 0x1U);
}

void gpio_pin_set_dir(enum IO_PIN_T pin, enum GPIO_DIR_T dir, uint8_t out_val)
{
    if (dir == GPIO_DIR_IN)
    {
        SYSCON->IO_EI |= (1U << pin);
        gpio_handle[0].base->OUTENCLR = (1U << pin);
    }
    else if (dir == GPIO_DIR_OUT)
    {
        if (out_val)
        {
            gpio_pin_set(pin);
        }
        else
        {
            gpio_pin_clr(pin);
        }
        gpio_handle[0].base->OUTENSET = (1U << pin);
    }
    else
    {
        SYSCON->IO_EI &= ~(1U << pin);
        gpio_handle[0].base->OUTENCLR = (1U << pin);
    }
}

void gpio_enable_irq(enum IO_PIN_T pin, enum GPIO_IRQ_TYPE_T irq_type, GPIO_IRQ_HANDLER_T irq_handler)
{
    switch (irq_type)
    {
        case GPIO_IRQ_TYPE_LOW_LEVEL:
            gpio_handle[0].base->INTPOLCLR = (1U << pin);
            gpio_handle[0].base->INTTYPECLR = (1U << pin);
            break;
        case GPIO_IRQ_TYPE_HIGH_LEVEL:
            gpio_handle[0].base->INTPOLSET = (1U << pin);
            gpio_handle[0].base->INTTYPECLR = (1U << pin);
            break;
        case GPIO_IRQ_TYPE_FALLING_EDGE:
            gpio_handle[0].base->INTPOLCLR = (1U << pin);
            gpio_handle[0].base->INTTYPESET = (1U << pin);
            break;
        case GPIO_IRQ_TYPE_RISING_EDGE:
            gpio_handle[0].base->INTPOLSET = (1U << pin);
            gpio_handle[0].base->INTTYPESET = (1U << pin);
            break;
    }

    gpio_handle[0].irq_handler[pin] = irq_handler;

    if (gpio_handle[0].irq_mask == 0)
    {
        NVIC_SetPriority(gpio_handle[0].irq, IRQ_PRIORITY_NORMAL);
        NVIC_ClearPendingIRQ(gpio_handle[0].irq);
        NVIC_EnableIRQ(gpio_handle[0].irq);
    }
    gpio_handle[0].irq_mask |= (1U << pin);

    gpio_handle[0].base->INTENSET = (1U << pin);
}

void gpio_disable_irq(enum IO_PIN_T pin)
{
    gpio_handle[0].base->INTENCLR = (1U << pin);
    gpio_handle[0].irq_mask &= ~(1U << pin);
    if (gpio_handle[0].irq_mask == 0)
    {
        NVIC_DisableIRQ(gpio_handle[0].irq);
        NVIC_ClearPendingIRQ(gpio_handle[0].irq);
    }
}

void GPIO_IRQHandler(void)
{
    uint32_t int_stat = gpio_handle[0].base->INTSTATUS;

    for (enum IO_PIN_T i = 0; i < IO_PIN_MAX; i++)
    {
        if ((int_stat & (1U << i)) && (gpio_handle[0].irq_handler[i]))
        {
            gpio_handle[0].irq_handler[i](i);
            gpio_handle[0].base->INTSTATUS = (1 << i);
        }
    }
}