/* * Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and * its subsidiaries and affiliates (collectly called MKSEMI). * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form, except as embedded into an MKSEMI * integrated circuit in a product or a software update for such product, * must reproduce the above copyright notice, this list of conditions and * the following disclaimer in the documentation and/or other materials * provided with the distribution. * * 3. Neither the name of MKSEMI nor the names of its contributors may be used * to endorse or promote products derived from this software without * specific prior written permission. * * 4. This software, with or without modification, must only be used with a * MKSEMI integrated circuit. * * 5. Any software provided in binary form under this license must not be * reverse engineered, decompiled, modified and/or disassembled. * * THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef USER_CONFIG_H_ #define USER_CONFIG_H_ /* =========================================================================================================================== */ /* ================ Silicon configuration ================ */ /* =========================================================================================================================== */ /** CPU model */ #define CPU_MK8000 /* =========================================================================================================================== */ /* ================ Board configuration ================ */ /* =========================================================================================================================== */ /** Enable radar presence detection processing locally, otherwise the radar raw data will be outputted by UART */ #define UWB_RADAR_DETECT_PROCESS_EN (1) /** Define radar data dump port */ #if UWB_RADAR_DETECT_PROCESS_EN == 0 #define DUMP_DATA_PORT UART_ID1 #endif /** Define trace port */ #define TRACE_PORT TRACE_PORT_UART0 /* =========================================================================================================================== */ /* ================ Driver configuration ================ */ /* =========================================================================================================================== */ // ACMP work mode #define ACMP_INT_MODE_EN (0) // ADC work mode #define ADC_INT_MODE_EN (0) #define ADC_DMA_MODE_EN (0) #define ADC_POLL_MODE_EN (1) // AES work mode #define AES_INT_MODE_EN (0) #define AES_DMA_MODE_EN (1) #define AES_POLL_MODE_EN (0) // Flash work mode #define FLASH_INT_MODE_EN (0) #define FLASH_DMA_MODE_EN (0) // I2C work mode #define I2C_INT_MODE_EN (0) #define I2C_POLL_MODE_EN (1) // LSP work mode #define LSP_INT_MODE_EN (0) // PWM work mode #define PWM_INT_MODE_EN (0) // RTC work mode #define RTC_FREE_COUNTER_EN (0) // SPI work mode #define SPI_INT_MODE_EN (0) #define SPI_DMA_MODE_EN (1) #define SPI_POLL_MODE_EN (1) // TRNG work mode #define TRNG_INT_MODE_EN (0) #define TRNG_POLL_MODE_EN (1) // UART work mode #define UART_INT_MODE_EN (0) #define UART_DMA_MODE_EN (1) #define UART_POLL_MODE_EN (0) // Dual Timer work mode #define TIMER0_INT_MODE_EN (1) #define TIMER1_INT_MODE_EN (1) // Timer work mode #define TIMER2_INT_MODE_EN (0) #define TIMER3_INT_MODE_EN (1) /* =========================================================================================================================== */ /* ================ Debug/TRACE configuration ================ */ /* =========================================================================================================================== */ /** Enable trace output */ #define TRACE_EN (1) /** Enable exception reboot */ #ifndef TRACE_REBOOT_EN #define TRACE_REBOOT_EN (1) #endif /** Enable standard format output */ #define TRACE_STD_LIB_EN (0) /** Configure trace level for modules: BOOT | TEST | UCI | UWB | APP | DRIVER | PHY | MAC */ #define TRACE_LVL_CONFIG_0 (0x44444444) /** Configure trace level for modules: CCC | FIRA | OS */ #define TRACE_LVL_CONFIG_1 (0x00000444) /** Configure trace buffer size (in bytes) */ #define TRACE_BUF_SIZE (1024) /* =========================================================================================================================== */ /* ================ Power configuration ================ */ /* =========================================================================================================================== */ /** Enable low power mode */ #ifndef LOW_POWER_EN #define LOW_POWER_EN (0) #endif /** Enable 32.768K crystal as low power mode clock source */ #ifndef XTAL32K_EN #define XTAL32K_EN (1) #endif /** Enable DC-DC */ #ifndef DCDC_EN #define DCDC_EN (1) #endif /** Enable BOR */ #ifndef BOR_EN #define BOR_EN (0) #endif /** Enable BOD */ #ifndef BOD_EN #define BOD_EN (0) #endif /** Enable UWB high performance mode, it will increase power consumption */ #ifndef HIGH_PERFORMANCE_MODE_EN #define HIGH_PERFORMANCE_MODE_EN (1) #endif /* =========================================================================================================================== */ /* ================ Clock configuration ================ */ /* =========================================================================================================================== */ /** Configure system clock source @ref enum CLOCK_ATTACH_TYPE_T */ #define SYS_CLK_SOURCE (CLOCK_62P4M_XTAL38P4M_TO_SYS_CLK) /** AHBCLK = SYSCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */ #define AHB_DIV (CLOCK_DIVIDED_BY_1) /** APBCLK = AHBCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */ #define APB_DIV (CLOCK_DIVIDED_BY_1) /** Configure 32K clock source @ref enum CLOCK_ATTACH_TYPE_T */ #if XTAL32K_EN #define CLK_32K_SOURCE (CLOCK_XTAL32K_TO_32K_CLK) #define LOW_POWER_CLOCK_PPM (50) #else #define CLK_32K_SOURCE (CLOCK_RCO32K_TO_32K_CLK) #define LOW_POWER_CLOCK_PPM (1000) #endif /** Enable system tick timer (period = 10ms), needed by OS */ #define SYS_TICK_EN (1) /* =========================================================================================================================== */ /* ================ UWB configuration ================ */ /* =========================================================================================================================== */ /** Enable Post-process filter */ #define FILTER_EN (0) /** Enable RSSI output */ #define RSSI_EN (1) /** Enable Channel status information output */ #define CSI_EN (0) /** Enable PDoA 3D */ #define PDOA_3D_EN (1) /** Enable AoA */ #define AOA_EN (0) /** Measure angle on 1 (responder side), 2 (initiator side), 3 (both sides), 0 (None) */ #define MEASURE_ANGLE_ON_ROLE (1) /** TX power level: 0 ~ 60 */ #define TX_POWER_LEVEL (36) /** Antenna ports combination, @ref macro definition RX_xPORTS_ANT_xxx */ #define RX_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2) /** Dynamic update RX main antenna, can be enabled only when 4 ports are in use */ #define DYNAMIC_UPDATE_MAIN_ANTENNA_EN (0) #if PDOA_3D_EN /// Antenna pattern #define ANT_PATTERN (ANT_PATTERN_SQUARE) /// Antenna layout, @ref enum ANT_LAYOUT_T #define ANT_LAYOUT (ANT_LAYOUT_HORIZONTAL) #else /// Antenna pattern #define ANT_PATTERN (ANT_PATTERN_LINEAR) #endif /** Enable load cap automatic tuning during ranging procedure */ #define XTAL_AUTO_TUNE_EN (1) /** Enable kalman filter as post process filter, FILTER_EN should be enabled meanwhile */ #define KF_EN (1) /** Velocity of propagation (%) */ #define VP_VAL (100) /* =========================================================================================================================== */ /* ================ UWB Radar configuration ================ */ /* =========================================================================================================================== */ /** Time Division Multiplexing Radar Ranging */ #define TDM_RANGING_AND_RADAR /** UWB radar STS segment length, 0:STS segment length 16, 1:STS segment length 32, 2:STS segment length 64 */ #define UWB_RADAR_STS_LENGTH (2) /** UWB radar pulse period, 0:16ns, 1:32ns, 2:64ns, 3:128ns, 4:256ns*/ #define UWB_RADAR_PULSE_PERIOD (2) /** UWB radar channel number: 5, 9 */ #define UWB_RADAR_CHANNEL_NUM (9) /** UWB radar rx filter gain level 0 ~ 21 */ #define UWB_RADAR_FILTRE_GAIN_LEVEL (14) /** UWB radar lna gain level 0 ~ 5 */ #define UWB_RADAR_LNA_GAIN_LEVEL (5) /** UWB radar tx power level 0 ~ 60 */ #define UWB_RADAR_TX_POWER_LEVEL (46) /** UWB radar tx pulse width 0:2ns (Bandwidth 500M), 1:0.92ns (Bandwidth 900M), 2: 0.75ns (Bandwidth 1.3G) */ #define UWB_RADAR_BANDWIDTH (2) /** 1TnR radar mdoe: 0: Single, 1: Overlay */ #define UWB_RADAR_1TNR_MODE 1 /** 1TnR mode RX port number */ #define UWB_RADAR_RX_PORT_NUM 1 /** UWB radar rx antenna start port @ref enum UWB_RX_ANT_T: UWB_RX_ANT_0, UWB_RX_ANT_1, UWB_RX_ANT_2 */ #define UWB_RADAR_RX_ANT_ID (UWB_RX_ANT_0) /** Enable UWB radar on role: 1 (responder side), 2 (initiator side), 3 (both sides), 0 (None) */ #define UWB_RADAR_ON_ROLE (1) /** Enable radar control by UCI */ #define UWB_RADAR_UCI_EN (0) /* ========================================== PPDU configuration ======================================== */ /** channel number: 2, 5, 9 */ #define UWB_CH_NUM (9) /** mean PRF: @ref enum PRF_MODE_T */ #define UWB_MEAN_PRF (PRF_62M4) /** preamble code index: 1 ~ 8, 9 ~ 24, 25 ~ 32 */ #define UWB_PREAMBLE_CODE_IDX (10) /** preamble duration: @ref enum PREAMBLE_DURATION_T */ #define UWB_PREAMBLE_DURATION (SYMBOLS_64) /** SFD ID: @ref enum SFD_ID_T */ #define UWB_SFD_ID (SFD2_LEN8) /** PSDU data rate: @ref enum PSDU_DATA_RATE_T */ #define UWB_PSDU_DATA_RATE (BPS_6M8) /** STS segment number: @ref enum STS_SEGMENTS_NUM_T */ #define UWB_STS_SEGMENT_NUM (STS_SEGMENTS_1) /** STS segment length: @ref enum STS_SEGMENTS_LENGTH_T */ #define UWB_STS_SEGMENT_LEN (STS_SEG_LEN64) /** Ranging frame packet type: @ref enum RFRAME_TYPE_T, if AoA is enabled, the frame should contain STS */ #define UWB_RFRAME_TYPE (SP3) /** Maximum PHY payload length */ #define PHY_PAYLOAD_LEN_MAX (127) /* ========================================== Timing configuration ======================================== */ /// Period prefetch time for event program from wakeup - 600us+ #define UWB_PERIOD_PREFETCH_TIME (US_TO_PHY_TIMER_COUNT(600)) /// Event prefetch time for event program - 300us #define UWB_EVT_PREFETCH_TIME (US_TO_PHY_TIMER_COUNT(300)) /// RX window open in advance time - 10us #define UWB_RX_OPEN_IN_ADVANCE (US_TO_PHY_TIMER_COUNT(10)) /// RX window - 400us #define UWB_RX_WINDOW (US_TO_PHY_TIMER_COUNT(400)) /** Ranging slot duration, unit: RSTU (1200 = 1ms), maximum: 65535 */ #define UWB_RANGING_SLOT_DURATION (3600) /** Ranging block duration, unit: ms */ #define UWB_RANGING_INTERVAL (96) /* =========================================================================================================================== */ /* ================ End ================ */ /* =========================================================================================================================== */ #endif /* USER_CONFIG_H_ */